Coordinate Mapping Circuit With Bit Interleaving and Demultiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing circuit for mapping texture coordinates to memory addresses in graphics processing units (GPUs) is complex due to extensive shifting and multiplexing, which increases silicon footprint and complexity, particularly in handling different size coordinates and requiring multiple control signals for multiplexers.
Innovation Solution
A circuit that interleaves all coordinate bits together before demultiplexing them into separate channels, using null bits for padding, reduces the need for shifting and multiplexing by aligning outputs simply through cascaded shift-and-combine circuitry, eliminating the need for right shifting and minimizing left shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive shifting and multiplexing is used to handle different size coordinates, then mapping accuracy is improved, but device complexity increases
Solution Approach 1:
The coordinate bits are segmented into groups based on their significance (most significant bits, least significant bits) and processed through separate channels. This segmentation allows each channel to handle specific bit ranges with appropriate shifting operations, improving mapping accuracy while controlling complexity through modular processing.
Solution Approach 2:
The patent transforms the problem from handling coordinates of different lengths in a single dimension to processing them in multiple dimensions by creating separate channels for different bit significance groups. This dimensional transformation allows parallel processing of MSB and LSB channels, achieving accurate mapping without requiring complex sequential multiplexing operations.
2Adaptability or versatility
If multiple control signals are used for multiplexers to handle different size coordinates, then adaptability is improved, but device complexity increases
Solution Approach 1:
The coordinate bits are pre-grouped into MSB and LSB channels before processing, with null bits预先 inserted to standardize the bit width. This preliminary organization eliminates the need for dynamic multiplexer control signals during operation, as the routing path is predetermined by the grouping structure, thereby reducing control complexity while maintaining adaptability to different coordinate sizes.
Solution Approach 2:
Instead of using multiplexers to dynamically select which coordinate bits to process based on control signals, the patent inverts the approach by using fixed routing paths where MSB channels and LSB channels are separately processed through dedicated pipelines. This inversion eliminates the need for control signals while maintaining the ability to handle different coordinate sizes through the fixed architectural design.
3Measurement precision
If extensive shifting operations are performed, then mapping precision is improved, but loss of time increases
Solution Approach 1:
The shifting operations in the MSB and LSB channels are performed continuously and simultaneously rather than sequentially. The MSB channel performs its shifting operations while the LSB channel performs its operations in parallel, maintaining continuous useful action across both channels. This parallel continuous processing achieves precise address mapping while minimizing processing time by eliminating sequential delays.
Data Source
AI summary
A circuit for mapping N coordinates to a 1D space receives N input bit-strings representing respective coordinates, which can be of different sizes; produces a grouped bit-string therefrom, in which the bits, including non-data bits, are grouped into groups of bits originating from the same bit position per group; and demultiplexes this into n=1 . . . N demultiplexed bit-strings, and sends each to a respective n-coordinate channel. The nth demultiplexed bit-string includes a respective part of the grouped bit-string that has n coordinate data bits and N-n non-data bits per group, and all other groups filled with null bits. Each but the N-coordinate channel includes bit-packing circuitry which packs down the respective demultiplexed bit-string by removing the non-data bits, and removing the same number of bits per group from the null bit.