Fault Detection Circuit for CoP Bonding Pad Chains

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Solution Overview

Problem

Existing semiconductor devices with a stacked structure, such as those with a Cell over Peripheral (CoP) structure, face challenges in efficiently detecting faults in bonding pads, which are critical for ensuring proper connectivity and functionality.

Innovation Solution

A semiconductor device with a CoP structure incorporates a test pad chain connected to fault detection circuits that include data input, data path, and data reset circuits to detect and locate faults in bonding pads by analyzing voltage levels and signal transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a stacked structure (CoP) is used to increase integration, then device functionality and capacity are improved, but fault detection capability in bonding pads deteriorates

Engineering Contradiction:
Improvedevice functionalityVSAvoidfault detection capability
Core Design Contradiction:
Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The test pad chain is divided into multiple segments with individual fault detection circuits at each stage. Each detection circuit independently monitors a specific segment of the bonding pad chain, allowing localized fault detection without requiring complete chain testing. This segmentation enables precise identification of fault locations while maintaining detection capability in the stacked CoP structure.

Inventive Principle:
Principle #1Segmentation

2Difficulty of detecting and measuring

If multiple fault detection circuits are added to detect bonding pad faults, then fault detection capability is improved, but device complexity increases

Engineering Contradiction:
Improvefault detection capabilityVSAvoiddevice complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

Multiple fault detection circuits are merged into a unified test pad chain structure where circuits are cascaded together. The output of one detection circuit feeds into the next, creating an integrated detection system that shares common signal paths and control logic. This merging approach enables comprehensive fault detection while minimizing the increase in overall device complexity through资源共享 and structural integration.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If comprehensive fault detection is implemented, then reliability is improved, but testing time increases

Engineering Contradiction:
ImprovereliabilityVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Fault detection circuits are configured to perform preliminary detection of bonding pad connectivity during the stacking process itself, before final device assembly and testing. The test pad chain is activated early in the manufacturing flow to identify and isolate faulty bonds, allowing defective structures to be rejected before committing additional processing time and resources. This preliminary action significantly reduces overall testing time while maintaining high reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260079196A1Semiconductor device including fault detection circuit
Publication Date: 2026.03.19 SAMSUNG ELECTRONICS CO LTD
  • US20260079196A1 patent drawing
  • US20260079196A1 patent drawing
  • US20260079196A1 patent drawing

AI summary

A semiconductor device includes a first structure including first test pads, a second structure disposed on the first structure and including second test pads that respectively correspond to the first test pads and form a test pad chain with the first test pads, a first terminal connected to one end of the test pad chain, a plurality of fault detection circuits connected to the test pad chain to detect a connection status of the test pad chain, and a second terminal connected to the other end of the test pad chain.