COP Memory Circuit Layout With Barrier Bypass Via Reliability
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Solution Overview
Problem
As memory cell sizes in integrated circuit devices are reduced to meet the demand for high integration in communication devices, the complexity of operation circuits and wiring structures increases, posing challenges for structural reliability and electrical characteristics.
Innovation Solution
An integrated circuit device with a COP (Cell Over Periphery) structure is developed, featuring a substrate with a peripheral wiring circuit, a barrier layer, and a memory cell array. The barrier layer includes a bypass hole and via, and is made of sequentially stacked conductive, insulating, and semiconductor material layers, providing structural support and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell sizes are reduced to increase integration, then integration capacity is improved, but structural reliability deteriorates
Solution Approach 1:
The patent transitions from a planar wiring structure to a three-dimensional structure by introducing vertical vias (contact holes) that penetrate through multiple insulating layers. This allows wiring to be routed in the vertical dimension, reducing congestion in the horizontal plane and enabling higher integration while maintaining structural integrity through properly designed via structures with barrier layers and plug materials.
Solution Approach 2:
The patent employs composite material structures in the wiring system, including combinations of conductive materials (copper, tungsten, aluminum) with insulating materials (silicon oxide, silicon nitride, low-k dielectrics). These composite structures provide both electrical connectivity and mechanical support, ensuring reliability while enabling dense integration through multi-layer interconnect architectures.
2Productivity
If memory cell sizes are reduced to increase integration, then integration capacity is improved, but wiring structure complexity increases
Solution Approach 1:
The patent divides the wiring structure into multiple discrete layers (first insulating layer, second insulating layer, third insulating layer) with dedicated vias for different routing functions. This segmentation allows independent optimization of each layer's routing path, simplifying the overall wiring design by breaking down complex interconnect requirements into manageable modular components.
Solution Approach 2:
By introducing vertical routing through contact holes that penetrate through stacked insulating layers, the patent adds a vertical dimension to wiring routing. This three-dimensional routing capability reduces the burden on horizontal wiring paths, simplifying the overall wiring structure while achieving high integration density.
3Reliability
If peripheral wiring circuit is surrounded by interlayer insulating layer, then electrical isolation is improved, but bypass via fabrication complexity increases
Solution Approach 1:
The patent forms the bypass via structure during the same fabrication sequence as the regular contact holes, using preliminary patterning and etching steps that define both types of vias simultaneously. The barrier layer and plug material deposition are performed in advance, allowing the bypass via to be created without requiring additional specialized processing steps, thus maintaining electrical isolation while simplifying fabrication.
Solution Approach 2:
The patent designs the bypass via to serve multiple functions: providing electrical isolation where needed, enabling routing paths for peripheral circuits, and maintaining structural support. By creating a universal via structure that can function as both an isolation element and a routing element, the patent reduces fabrication complexity while achieving the desired electrical isolation performance.
Data Source
AI summary
An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.