CoP Memory Core Layout for Compact DRAM Peripheral Routing
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Solution Overview
Problem
Existing DRAM devices face limitations in size reduction due to the inefficiencies in arranging circuits for driving memory cell arrays, particularly with the use of vertical channel transistors, as conventional open bitline structures and increased implementation difficulty hinder further miniaturization.
Innovation Solution
A memory core circuit with a cell on periphery (CoP) structure is implemented, where a memory cell array is surrounded by a core control circuit, with sub peripheral circuits divided into edge and central regions, and bitline sense amplifiers and wordline drivers are strategically positioned to optimize circuit arrangement, allowing for efficient control and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional open bitline structure is used, then circuit arrangement is simplified, but device size reduction is limited
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture where memory cell arrays are positioned above core control circuits. This vertical stacking enables simultaneous optimization of both circuit arrangement simplicity and device size reduction by utilizing the third dimension (height) rather than expanding in the planar direction.
Solution Approach 2:
The patent implements a nested structure where core control circuits are embedded within or beneath memory cell arrays, forming a hierarchical arrangement. This nesting allows compact integration of control functions within the memory structure itself, achieving size reduction while maintaining manufacturing simplicity through modular design.
2Area of moving object
If vertical channel transistor is used, then cell transistor size is reduced, but implementation difficulty increases
Solution Approach 1:
The patent divides the memory device into distinct functional layers: memory cell arrays in upper regions and core control circuits in lower regions. This segmentation allows independent optimization of each layer, enabling the use of vertical channel transistors in memory cells for size reduction while keeping control circuit implementation in the conventional planar domain where manufacturing is more straightforward.
Solution Approach 2:
The patent applies different structural qualities to different regions: vertical channel transistors are used locally in memory cell arrays where space optimization is critical, while core control circuits use conventional planar transistors where implementation simplicity is prioritized. This local differentiation resolves the contradiction by allowing VCTs only where they provide the most benefit.
3Volume of moving object
If core control circuit is efficiently disposed, then device size is reduced, but circuit complexity increases
Solution Approach 1:
By moving core control circuits to the vertical dimension (below memory cell arrays), the patent achieves compact planar footprint without increasing overall circuit complexity. The separation into vertical layers simplifies interconnections compared to planar integration, as control signals can be routed through dedicated vertical vias rather than complex lateral interconnects.
Data Source
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AI summary
A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits under the sub cell arrays. The sub peripheral circuits are divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are disposed in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region. At least a portion of device peripheral circuits configured to control the memory core circuit is disposed in a rest region other than the sense amplifier region and the wordline driver region.