Cell Over Periphery Memory Device Wiring Architecture
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Solution Overview
Problem
The reduction of vertical memory device size is limited due to the need for an interface to connect with peripheral circuits for communication and power supply, which hinders further miniaturization.
Innovation Solution
A memory device with a cell over periphery (COP) structure, where a peripheral circuit is placed on a substrate and a memory cell array is stacked on top, with a wiring layer that includes power wirings and a wiring electrically connected to transistors, allowing for flexible power selection and efficient design modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical memory device structure is used to increase storage capacity, then the storage capacity within a small structure is improved, but the device size reduction is limited due to the need for peripheral circuit interfaces
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where memory cell arrays are vertically stacked above the peripheral circuit region. This vertical stacking approach utilizes the third dimension (height) to increase storage capacity without proportionally increasing the footprint area, effectively resolving the contradiction between storage capacity and device size.
Solution Approach 2:
The wiring layer is designed with multi-functionality, where the same wiring structure serves both as interconnect for the peripheral circuit and as power supply for the memory cell arrays. The first wiring electrically connected to the first transistor can be selectively connected to different power wirings (first power wiring or second power wiring), providing flexible power distribution across different operational modes while using a unified wiring infrastructure.
2Ease of manufacture
If the wiring layer is designed with flexible power selection capability, then the ease of manufacture and design modification is improved, but the device complexity increases
Solution Approach 1:
The wiring configuration incorporates dynamic reconfigurability through switchable connections. The first wiring can be dynamically connected to either the first power wiring or the second power wiring based on operational requirements. This dynamic switching capability allows the device to adapt between different power modes (e.g., normal operation vs. power-saving mode) without requiring physical redesign, thereby improving ease of manufacture and design flexibility while managing complexity through controlled reconfigurability.
Data Source
AI summary
A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.