Cell-on-peri non-volatile memory with stacked upper substrates
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Solution Overview
Problem
As memory devices become more complex with reduced cell sizes for higher integration, there is a demand for improved electrical characteristics and increased capacity, which existing technologies struggle to meet due to complex operating circuits and wiring in memory devices.
Innovation Solution
A non-volatile memory device structure is implemented with a cell-on-peri (COP) configuration, where the memory cell array is stacked on top of the peripheral circuit, reducing the overall area and enhancing integration by using a layered substrate structure with a first and second upper substrate separated by a dielectric layer, supporting the memory cell array and peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced for higher integration, then memory capacity and integration are improved, but operating circuits and wiring become more complex
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where memory cell arrays are formed on upper substrates positioned above peripheral circuits. This vertical stacking enables higher integration density without proportionally increasing wiring complexity, as connections are established through vertical vias rather than extensive lateral routing.
Solution Approach 2:
The memory device is divided into functionally separate regions: peripheral circuits on a lower substrate and memory cell arrays on one or more upper substrates. This segmentation allows each region to be optimized independently, with peripheral circuits occupying the lower layer and memory cells stacked above, reducing interference and simplifying interconnect design.
2Quantity of substance
If memory devices are highly integrated, then capacity increases, but area occupied by the device decreases
Solution Approach 1:
The invention utilizes vertical stacking to achieve high memory capacity within a reduced footprint. Multiple memory cell arrays are positioned at different heights above the peripheral circuit substrate, effectively using the third dimension (height) to increase storage capacity without expanding the planar area of the device.
Solution Approach 2:
The structure implements a nested arrangement where memory cell arrays on upper substrates are positioned directly above peripheral circuits on the lower substrate. This nesting maximizes space utilization by stacking functional blocks vertically, allowing the device to achieve high integration density within a compact form factor.
3Device complexity
If peripheral circuits and memory cell arrays are placed on the same substrate, then wiring is simplified, but area consumption increases
Solution Approach 1:
The patent resolves the area-wiring tradeoff by separating peripheral circuits and memory cell arrays into different vertical layers. Peripheral circuits reside on the lower substrate while memory cell arrays are formed on upper substrates positioned above. This vertical separation reduces the planar area required while managing wiring complexity through controlled inter-layer connections via vias and contact holes.
Data Source
AI summary
A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.