COP Memory Layout With Vertical Channels for Higher Density
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing storage capacity and integration density while optimizing chip size and reducing manufacturing costs.
Innovation Solution
The implementation of a cell over periphery (COP) structure, where peripheral circuits are disposed under memory cells, utilizing vertical and horizontal channel transistors to optimize chip size by distributing peripheral circuits in upper and lower middle regions, enhancing heat resistance and timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If peripheral circuits are disposed under memory cells using COP structure, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture by disposing peripheral circuits underneath memory cell regions. This vertical stacking enables memory cells to be positioned over peripheral circuits, effectively utilizing the third dimension (depth) to increase integration density without expanding the lateral chip footprint.
Solution Approach 2:
The semiconductor device is divided into multiple distinct regions: a first region containing memory cell arrays, a second region containing peripheral circuits disposed underneath the first region, and a third region containing additional peripheral circuits. This segmentation allows independent optimization and manufacturing of different functional blocks while achieving high integration through their spatial arrangement.
2Area of stationary object
If vertical channel transistors are used in memory cell arrays, then chip area is reduced, but timing margins decrease
Solution Approach 1:
The patent employs different transistor types in different regions to optimize local performance. Vertical channel transistors are used in the memory cell arrays where area efficiency is critical, while horizontal channel transistors are used in peripheral circuit regions where timing margins and signal drive capability are more important. This localized optimization resolves the contradiction by allowing each region to use the transistor type best suited for its function.
Data Source
AI summary
A semiconductor memory device with a cell over periphery (COP) structure, which includes a first semiconductor structure, and a second semiconductor structure disposed on a lower side of the first semiconductor structure. The first semiconductor structure includes a memory region, a first region, a memory cell array disposed in the memory region and including vertical channel transistors, and first peripheral circuits disposed in the first region and including vertical channel transistors or horizontal channel transistors. The second semiconductor structure includes a second region, a third region, second peripheral circuits disposed in the second region, which is on a lower side of the first region, and including horizontal channel transistors, and third peripheral circuits disposed in the third region, which is on a lower side of the memory region, and including horizontal channel transistors.