COP Memory Layout With Vertical Contacts for Higher Array Density
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Solution Overview
Problem
The existing vertical memory devices face limitations in size reduction due to the use of vertical contacts for connecting memory cell arrays and peripheral circuits, which restricts the integration and memory capacity per unit area.
Innovation Solution
A nonvolatile memory device with a cell over periphery (COP) structure is implemented, where peripheral circuits are disposed in a peripheral region and memory cell arrays are stacked over them, utilizing vertical contacts to connect bitlines and page buffers, and half memory blocks are placed in overhead regions to increase memory capacity per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical contacts are used to connect memory cell arrays and peripheral circuits, then electrical connection is achieved, but device size reduction is limited
Solution Approach 1:
The patent transitions from planar connection to vertical connection by stacking memory cell arrays over peripheral circuits in the third dimension. This allows electrical connections to be made through vertical contacts that penetrate through the substrate, enabling three-dimensional integration and reducing the footprint area of the device while maintaining all necessary electrical connections.
Solution Approach 2:
The patent implements a nested structure where memory cell arrays are stacked over peripheral circuits, with vertical contacts penetrating through the memory cell arrays to reach the peripheral circuits below. This nesting arrangement allows multiple functional layers to be integrated within a compact volume, achieving high-density integration without proportionally increasing device area.
2Quantity of substance
If memory cell arrays are stacked vertically to increase integration, then memory capacity per unit area increases, but overhead regions reduce available memory space
Solution Approach 1:
The patent applies local quality by placing overhead regions selectively at specific locations where vertical contacts are required for electrical connections, rather than uniformly across the entire device. This allows the majority of the stacked memory cell arrays to be used for storage, while minimizing the impact of overhead regions on total memory capacity.
Solution Approach 2:
The patent segments the device into distinct functional regions: peripheral circuits at the bottom, vertically stacked memory cell arrays in the middle, and overhead regions only at specific locations for vertical contacts. This segmentation allows independent optimization of each region, maximizing memory capacity while maintaining necessary electrical connections.
Data Source
AI summary
A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.