COP Memory Device Vertical Pass Transistor Integration
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Solution Overview
Problem
As memory devices become more integrated and capacitive, the increased number of word lines stacked vertically leads to a larger chip size due to the increased number of pass transistors, complicating the operation and wiring structure, and making it challenging to maintain a compact design.
Innovation Solution
The implementation of a memory device with a cell over periphery (COP) structure, where the pass transistor circuit is arranged in a stair area of the word lines, allowing for vertical pass transistors to be integrated without increasing the chip size, and the memory cell array is stacked with pass transistors and row decoders in separate semiconductor layers to optimize space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked vertically is increased to increase integration, then memory capacity is improved, but chip size increases due to increased number of pass transistors
Solution Approach 1:
The patent transitions from a planar arrangement of pass transistors to a three-dimensional structure by stacking pass transistors vertically in the stair area. This vertical stacking allows multiple pass transistors to share the same horizontal footprint, thereby increasing memory capacity without proportionally increasing chip area.
Solution Approach 2:
The patent implements a nested structure where pass transistors are stacked within the stair area formed by the word line configuration. The vertical pass transistors are positioned within the three-dimensional space created by the staggered word line arrangement, effectively nesting functional elements within the structural framework.
2Quantity of substance
If more pass transistors are added to support increased vertical word lines, then memory integration is improved, but operation circuit complexity increases
Solution Approach 1:
The patent merges the functions of multiple pass transistors into a compact vertical stack within the stair area. By combining multiple transistor functions into a single vertical column, the patent reduces the horizontal spread of the operation circuit while maintaining the required memory integration capacity.
3Ease of manufacture
If pass transistors are arranged in a traditional planar layout, then ease of manufacture is maintained, but horizontal area occupied by peripheral circuit increases
Solution Approach 1:
The patent moves the pass transistor arrangement from a two-dimensional planar layout to a three-dimensional vertical stack. This dimensional transition reduces the horizontal footprint of the peripheral circuit while maintaining manufacturability through standard vertical stacking processes compatible with existing semiconductor fabrication techniques.
Data Source
AI summary
A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.