3D Nonvolatile Memory Decoder Layout for Smaller COP NAND
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Solution Overview
Problem
Existing vertical memory devices face limitations in reducing size and manufacturing cost due to the inclusion of peripheral circuits and wiring structures, hindering high integration and electrical performance.
Innovation Solution
A nonvolatile memory device with a COP (cell over periphery) or BVNAND structure where the peripheral circuit is formed below and the memory cell array is stacked on top, allowing for separate formation of pass transistors and drivers, enhancing placement freedom and reducing circuit region and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If peripheral circuits and wiring structures are included in vertical memory devices, then electrical connection and driving functionality are achieved, but device size cannot be reduced
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing the memory cell array vertically above the peripheral circuit region. This vertical arrangement allows both the memory array and peripheral circuits to coexist within a compact footprint, significantly reducing the overall device area while maintaining all necessary electrical connection and driving functionalities.
Solution Approach 2:
The memory cell array is nested within the vertical space above the peripheral circuit region, with word lines extending downward to interface with the peripheral circuits. This nested configuration allows the memory array to be positioned within the footprint of the peripheral circuits, maximizing space utilization and minimizing the total device volume.
2Ease of manufacture
If pass transistors and drivers are formed together, then manufacturing process is simplified, but placement freedom and integration are limited
Solution Approach 1:
The address decoder circuit is segmented into two distinct functional regions: a first region containing pass transistors that are closely coupled with the memory cell array, and a second region containing drivers that are positioned independently. This segmentation allows each region to be optimized for its specific function while maintaining overall manufacturing simplicity through separate formation processes.
Solution Approach 2:
Different regions of the address decoder are assigned different layout patterns tailored to their specific functional requirements. The pass transistor region uses a layout optimized for proximity to the memory array and signal routing, while the driver region uses a layout optimized for control signal distribution. This local optimization enhances placement freedom and electrical performance without complicating the overall manufacturing process.
Data Source
AI summary
A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.