Co-Packaged Secondary FET Layout for Lower Converter Parasitics
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Solution Overview
Problem
Power converters using transformers to alter output voltage face challenges in minimizing parasitic losses and component area usage due to the separate integration of field-effect transistors (FETs) in primary and secondary circuits.
Innovation Solution
The integration of co-packaged secondary FETs within a single electronic package, connected between the transformer and inductor, and to ground, reduces parasitic losses and minimizes the area occupied on a circuit board by forming a compact RLC circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate integration of FETs in primary and secondary circuits is used, then device complexity is reduced and ease of manufacture is improved, but parasitic losses increase and component area increases
Solution Approach 1:
The patent combines the first FET and second FET into a single integrated circuit package, merging previously separate components into one unified device. This integration reduces the physical distance between components, minimizing parasitic inductance and resistance in interconnect paths, thereby reducing parasitic losses while managing the increased manufacturing complexity through standardized packaging processes
2Area of stationary object
If separate integration of FETs is used, then manufacturing process is simpler, but board area occupied by components increases
Solution Approach 1:
By integrating both FETs into a single circuit package, the patent significantly reduces the total board area required compared to mounting separate FETs. The consolidated package occupies less space while maintaining electrical performance, and the manufacturing process is simplified through standardized package mounting procedures rather than multiple discrete component installations
3Loss of energy
If co-packaged FETs are integrated, then parasitic losses are reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The integration of FETs into a co-packaged structure reduces parasitic losses by minimizing interconnect path lengths and reducing parasitic inductance. The manufacturing complexity is managed through standardized integrated circuit packaging techniques that are well-established in the industry, allowing for efficient production despite the increased integration level
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency of power converters by reducing parasitic losses and minimizing the board area, leading to improved performance and reduced manufacturing complexities.
Implementation Method 1
The transformer can include a primary inductor and a secondary inductor magnetically coupled to each other. The amount in which voltage is increased or decreased can be based on a ratio between the size (e.g., winding size) of the primary and secondary inductors.
Implementation Method 2
The first FET can be coupled between the transformer and the inductor. The second FET can be coupled between the first FET and ground.
Data Source
AI summary
A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.