Co-Packaged Optical Interfaces for High Radix Switch ASICs
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Solution Overview
Problem
Current data center and high-performance computing infrastructure faces limitations in networking due to constrained switch ASIC I/O bandwidth, which is exacerbated by the inability of semiconductor industry to keep up with data center bandwidth growth, leading to high Radix requirements on packet ASICs and increased power consumption.
Innovation Solution
The implementation of co-packaged optical interfaces with Photonic Integrated Circuits (PICs) integrated into ASICs, utilizing optical or electrical cross-connect systems to break out multiple data streams and increase the fan-out (radix) of optical connections, allowing for higher I/O capability and connectivity to more devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple ASICs are stacked into larger boxes to increase I/O bandwidth, then the apparent I/O capacity increases, but the problem is merely hidden rather than solved and device complexity increases
Solution Approach 1:
The patent combines electrical switch ASIC and optical I/O PIC into a single co-packaged unit, merging previously separate components (electrical switching fabric and optical interfaces) into one integrated system. This integration solves the I/O bandwidth limitation by bringing optical capabilities directly to the ASIC without requiring multiple stacked ASICs, thereby increasing capacity while reducing overall system complexity.
Solution Approach 2:
The patent introduces an optical I/O PIC as an intermediary component that bridges the electrical switch ASIC and optical fiber networks. This intermediary enables high-bandwidth optical communication while keeping the electrical switching logic separate, solving the bandwidth constraint without requiring complex multi-ASIC architectures.
2Quantity of substance
If packet ASIC Radix is increased to handle growing data center bandwidth, then networking capacity increases, but semiconductor packaging pin limits and lithography constraints prevent further scaling
Solution Approach 1:
The patent segments the networking function into two separate but co-packaged components: an electrical switch ASIC handling packet switching logic and an optical I/O PIC handling high-speed optical interfaces. This segmentation allows each component to be optimized independently for its specific function while overcoming the packaging pin limits that constrain monolithic high-Radix ASIC designs.
Solution Approach 2:
The patent transitions from purely electrical interconnects to optical interconnects by introducing photonic integrated circuits. This dimensional change from electrical to optical domain enables significantly higher bandwidth capacity without being constrained by traditional semiconductor packaging pin limits and lithography resolution constraints that bound electrical signal performance.
3Quantity of substance
If electrical I/O bandwidth is increased to meet data center requirements, then networking capacity increases, but power consumption increases super-linearly
Solution Approach 1:
The patent replaces electrical signal transmission with optical signal transmission for high-bandwidth I/O interfaces. This substitution eliminates the super-linear power consumption growth associated with electrical signaling at high speeds and high bandwidths, as optical transmission in fiber has significantly lower power requirements for achieving the same data rates.
4Quantity of substance
If optical interfaces are integrated directly into electronic switch ASIC, then I/O bandwidth and connectivity increase, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements co-packaging where the optical I/O PIC is nested within or adjacent to the electrical switch ASIC package. This nested arrangement provides the benefits of tight integration (high I/O connectivity, short interconnect lengths) while maintaining separate manufacturing processes for each component, thereby reducing the manufacturing complexity compared to fully monolithic integration.
Data Source
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AI summary
Systems and methods increase the fan-out (radix) of optical connections that are co-packaged with electric circuits, e.g., Application-Specific Integrated Circuits (ASICs). Optical or electrical techniques are presented to break out multiple data streams from a Photonic Integrated Circuit (PIC) integrated with an ASIC. This provides the ability to increase the I/O capability (radix) of an ASIC, allowing the ASIC to connect to a larger number of devices (e.g., servers). A cross- connect system includes one or more cross-connect devices optically interconnected to 1) a plurality of switches with each switch connected to one or more subtending servers, and 2) a plurality of switch circuits having Photonic Integrated Circuits (PICs) integrated therewith, each of the one or more cross-connect devices is configured to provide fan-out of the plurality of switches between the plurality of switch circuits to increase a number of the subtending servers.