Co-Packaged Optics Substrate Layout for EIC-PIC Thermal Integration
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Solution Overview
Problem
Forming connections between substrates in semiconductor devices poses challenges, particularly in integrating electronic integrated circuits (EICs) and photonic integrated circuits (PICs), which can lead to difficulties in thermal, physical, and electrical protection, as well as increased computational complexity.
Innovation Solution
A substrate with attachment locations for EICs and PICs, including a bridge for electrical connection, redistribution layers, optical fiber connections, and thermal vias for cooling, allows for efficient integration and communication between EICs and PICs, using a combination of glass or silicon substrates and embedded photonic integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If connections are formed between substrates to integrate EICs and PICs, then computational power is increased, but thermal management and physical protection become more difficult
Solution Approach 1:
The patent divides the integrated circuit system into separate EIC and PIC substrates, each optimized for its specific function. The EIC substrate handles electronic processing while the PIC substrate handles photonic operations, allowing independent thermal management strategies for each substrate type.
Solution Approach 2:
The patent introduces intermediate components such as redistribution layers and bonding interfaces that facilitate thermal transfer between substrates. These intermediary structures enable heat dissipation pathways while maintaining electrical and optical connections between EIC and PIC components.
2Power
If multiple integrated circuits are integrated on multiple substrates, then computational capabilities are enhanced, but packaging and protection complexity increases
Solution Approach 1:
The patent designs the substrate structure to serve multiple functions simultaneously: providing mechanical support, enabling electrical connections through redistribution layers, facilitating optical coupling, and offering thermal management pathways. This multi-functionality reduces the need for separate protective and functional components.
Solution Approach 2:
The patent combines multiple protective and functional layers into integrated packaging structures. The packaging encapsulates both EIC and PIC substrates together with their interconnections, creating a unified protected unit that simplifies handling and deployment while maintaining internal complexity for high computational performance.
3Productivity
If EICs and PICs are connected on the same substrate, then integration efficiency is improved, but electrical and optical connection difficulties arise
Solution Approach 1:
The patent applies different connection methodologies in different regions of the substrate. Electrical connections are established through conductive redistribution layers and vias in specific areas, while optical connections are facilitated through transparent or waveguide structures in other regions. This localized approach optimizes each connection type for its specific requirements.
Solution Approach 2:
The patent transitions from planar two-dimensional connections to three-dimensional vertical connections using stacked substrates and through-substrate vias. This dimensional change allows electrical and optical signals to traverse between EIC and PIC layers vertically, reducing lateral routing complexity and enabling higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables effective electrical and optical signal transmission between EICs and PICs, providing thermal management and protection, enhancing computational power and efficiency through hybrid transceivers.
Implementation Method 1
an optical fiber connection may extend between a surface of the substrate and the first photonic integrated circuit
Implementation Method 2
a thermal via may thermally couple the first photonic integrated circuit to the fluid cooling channel
Implementation Method 3
a fluid cooling channel may be formed within the substrate
Data Source
AI summary
Systems, methods and devices disclosed herein may include a substrate having a first attachment location and a second attachment location, a first photonic integrated circuit may be mounted within the first attachment location, and a bridge may be mounted within the second attachment location. A first compute device may be mounted on the substrate and at least partially over the first attachment location and the second attachment location.