Coplanar Bump Power Module for Thin Low-Parasitic Buck Converters
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Solution Overview
Problem
Existing power MOSFET packages are too thick for emerging applications, burdened with parasitic electrical and thermal resistances, and require complex assembly processes, which hinder achieving maximum thermal and electrical efficiencies and are costly.
Innovation Solution
A two-strata assembly of FET chips attached side-by-side on a low-cost conductive flat carrier with coplanar conductive bumps for direct attachment to a PCB, eliminating leadframes and clips, and allowing for heat sink attachment, reducing parasitic resistances and inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional leadframe and wire bond assembly is used, then electrical connections are established, but device thickness increases to several millimeters and parasitic inductance increases
Solution Approach 1:
The patent removes the traditional leadframe structure and wire bonds from the assembly. Instead, it uses a substrate with directly formed conductive bumps that make contact with the power MOSFET terminals, eliminating the intermediate connection elements that contribute to parasitic inductance and device thickness.
Solution Approach 2:
The patent integrates the substrate, conductive bumps, and power MOSFET assembly into a unified structure. The conductive bumps are formed directly on the substrate and make contact with the MOSFET terminals, merging the connection function into the substrate itself rather than using separate leadframe and wire bond components.
2Length of moving object
If leadframe with divided pad is used for flip-assembly, then device thickness is reduced to about 1.5 mm, but heat sink attachment is prevented because the pad is divided into two portions
Solution Approach 1:
The patent segments the conductive connection function from the thermal management function. The conductive bumps provide electrical connection, while a separate coplanar contact surface on the substrate provides thermal connection for heat sink attachment, allowing both functions to coexist without interference.
Solution Approach 2:
The substrate acts as an intermediary between the power MOSFET and the heat sink. It provides both electrical connection through conductive bumps and thermal connection through its coplanar contact surface, mediating both functions in a single component rather than requiring direct pad-to-heat-sink contact.
3Device complexity
If connecting clips and wire bonds are avoided with flip-assembly, then assembly complexity is reduced, but all three MOSFET terminals cannot be attached to PCB because the leadframe pad is remote from the PCB
Solution Approach 1:
The patent transitions from a vertical stacking arrangement (where terminals are at different heights requiring clips) to a coplanar arrangement where all MOSFET terminals and the substrate contact surface lie in the same plane. This allows direct attachment to the PCB without requiring vertical extension elements like clips or remote leadframe pads.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in thinner packages with reduced parasitic resistances and inductances, improved efficiency, and cost savings, enabling direct implementation into PCBs without modifying footprints, and enhanced thermal management.
Implementation Method 1
coplanar conductive bumps for direct attachment to a PCB, eliminating leadframes and clips, and allowing for heat sink attachment, reducing parasitic resistances and inductances
Implementation Method 2
A two-strata assembly of FET chips attached side-by-side on a low-cost conductive flat carrier with coplanar conductive bumps for direct attachment to a PCB
Data Source
AI summary
A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.