Multi-chip Package with Coplanar Carriers and Exposed Terminals
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Solution Overview
Problem
Current multi-chip modules face challenges with bulkiness, complex signal routing, difficulty in testing individual ICs before assembly, and inefficiencies in using known-good-die (KGD), leading to increased costs and assembly defects.
Innovation Solution
A multi-chip package system with coplanar carriers and a package encapsulation that exposes terminals, allowing for easier testing and connection of integrated circuit dies without additional connection structures, and enabling a thinner profile and higher pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple IC chips are mounted on a single substrate to increase packaging density, then the number of devices per package increases, but the module becomes bulky and requires complex routing structures
Solution Approach 1:
The patent transitions from planar mounting of multiple chips on a single substrate to a vertical stacked configuration where chips are arranged in multiple layers along the vertical dimension. This dimensional change allows higher device density without increasing the horizontal footprint, thereby reducing overall module bulk while accommodating more IC chips.
Solution Approach 2:
The patent implements a nested structure where multiple carrier substrates are stacked vertically, with each carrier holding IC chips. The carriers themselves are nested within a common package structure, creating a hierarchical arrangement that maximizes space utilization and reduces the overall module volume while maintaining high device count.
2Reliability
If die are tested individually before assembly to ensure known-good-die, then reliability improves, but the small bond pads make testing difficult
Solution Approach 1:
The patent introduces an intermediary carrier substrate that facilitates testing of individual die before final assembly. The carrier provides enlarged test pads and appropriate test structures that make electrical testing feasible, acting as a mediator between the small-bond-pad die and the test equipment, thereby enabling reliable KGD verification without direct testing of the tiny die pads.
3Adaptability or versatility
If complex routing structures and interposers are used to connect multiple ICs, then signal routing capability increases, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the routing function into separate segments, with each carrier substrate handling its own local interconnections and routing. This segmentation eliminates the need for a single complex global routing structure, as each carrier independently manages signal distribution to its mounted IC chips, thereby reducing overall system complexity while maintaining routing versatility.
4Quantity of substance
If multiple IC chips are assembled on a substrate, then circuit density increases, but assembly defects increase due to inability to test before assembly
Solution Approach 1:
The patent performs preliminary testing of individual IC chips while they are still mounted on their respective carrier substrates, before the final assembly process. This preliminary action allows defects to be identified and rejected chips to be removed, ensuring that only known-good-die proceed to final assembly, thereby maintaining high circuit density while preventing assembly defects from propagating.
Data Source
AI summary
A multi-chip package system is provided including providing a first carrier having a first integrated circuit die thereover, providing a second carrier, placing the first carrier coplanar with the second carrier, and molding a package encapsulation around and exposing the first carrier.