Coplanar Semiconductor Package Structure for Heat and Power Noise
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently dissipating heat and maintaining power integrity due to limitations in heat dissipation structures and power supply noise, particularly in stacked chip configurations.
Innovation Solution
A semiconductor package design featuring a substrate, interposer, silicon capacitor layer with embedded capacitors, and a molding layer that surrounds the chip stack, allowing for improved heat dissipation and power integrity by ensuring coplanar top surfaces of chips and layers, which simplifies manufacturing processes and reduces noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If heat dissipation structures are added to semiconductor packages, then heat dissipation efficiency is improved, but device complexity increases
Solution Approach 1:
The patent combines heat dissipation functionality with the existing substrate structure by integrating heat dissipation patterns directly into the substrate layer. This merging approach allows heat dissipation to be achieved without adding separate, complex heat dissipation components, thereby improving heat dissipation efficiency while avoiding increased device complexity.
Solution Approach 2:
The substrate is designed to serve multiple functions simultaneously: it provides mechanical support, electrical connections, and heat dissipation. By making the substrate multi-functional, the patent eliminates the need for separate dedicated heat dissipation structures, thus improving heat dissipation efficiency without increasing overall device complexity.
2Reliability
If power supply structures are added to improve power integrity, then power integrity is improved, but device complexity increases
Solution Approach 1:
The patent integrates power integrity enhancement features directly into the existing substrate and interposer structures by incorporating power supply patterns and grounding patterns into the substrate layers. This merging approach improves power integrity without requiring separate, complex power supply structures.
Solution Approach 2:
The substrate is divided into multiple functional layers with distinct power supply patterns, grounding patterns, and signal transmission patterns. This segmentation allows each layer to be optimized for its specific function while working together as an integrated system, improving power integrity through structured layering rather than adding complex external structures.
3Manufacturing precision
If coplanar top surfaces are ensured for all chips and layers, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent designs the substrate and interposer structures with equipotential top surfaces, where all critical surfaces (chip tops, interposer top, substrate top) are maintained at the same elevation plane. This equipotential design simplifies the manufacturing process by providing a uniform reference plane for mounting and packaging operations, improving coplanarity precision without adding complex adjustment mechanisms.
Solution Approach 2:
The patent controls the thickness parameters of substrate layers and interposer structures during manufacturing to ensure that all top surfaces align coplanarly. By precisely controlling these dimensional parameters in the design stage, the patent achieves high coplanarity precision through parameter optimization rather than through complex post-manufacturing adjustment structures.
Data Source
AI summary
A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.