Semiconductor Package Coplanar Conductive Vias
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Solution Overview
Problem
In semiconductor package structures, conductive vias formed by plating often result in dimple or protrusion shapes due to electrolyte composition, leading to non-planar surfaces that hinder proper placement of circuit layers, causing defects in circuit structures, especially when line widths and spaces are small.
Innovation Solution
A semiconductor package structure with a conductive element having a first portion with a surface coplanar with the dielectric layer and a second portion with a recessed surface, allowing for proper disposition of circuit structures and preventing defects by ensuring a flat surface for trace formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive via is formed by plating with electrolyte, then electrical connection between different layers is achieved, but the conductive element forms dimple shape or protrusion shape resulting in non-planar surface
Solution Approach 1:
A planarization layer is formed over the substrate before the conductive element is formed, creating a flat surface that compensates for the non-planar shape that will later form during plating. This preliminary action ensures that the circuit layer can be properly disposed on the surface even though the conductive element will have dimple or protrusion shapes.
Solution Approach 2:
The planarization layer is specifically positioned to cover only the areas where non-planarity occurs on the conductive element. This localized compensation approach maintains surface flatness precisely where needed for circuit layer placement, while allowing the conductive element to retain its functional plating structure.
2Ease of manufacture
If conductive element has non-planar surface with dimple or protrusion, then plating process is completed, but circuit layer cannot be properly disposed on or above the conductive via
Solution Approach 1:
The planarization layer is formed in advance to create a flat working surface. This preliminary structural preparation enables proper circuit layer placement by compensating for the non-planar geometry that will develop during the plating process, making the system easier to manufacture with standard circuit fabrication techniques.
3Quantity of substance
If electrolyte composition is used for plating, then conductive element is formed, but the composition causes dimple or protrusion shape formation
Solution Approach 1:
Instead of attempting to change the electrolyte composition to prevent dimple or protrusion formation, the invention accepts these shapes as inevitable byproducts of effective plating and uses a planarization layer to compensate. This converts the harmful geometric effect into a manageable condition that can be overcome with an additional structural element.
Solution Approach 2:
The invention changes the structural parameter of the overall system by adding a planarization layer, rather than changing the chemical parameters of the electrolyte. This allows the plating process to continue with its effective material deposition while the added layer compensates for the geometric irregularities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The coplanar surface of the conductive element enables smooth deposition of circuit traces, reducing defects and ensuring reliable electrical connections even at small line widths and spaces, thereby enhancing the overall performance and reliability of the semiconductor package.
Implementation Method 1
The formation of the conductive via may include forming a hole on a substrate, and then forming a conductive element in the hole by plating
Data Source
AI summary
A semiconductor package structure includes a first dielectric layer, a conductive element, a first circuit structure, a semiconductor die and an encapsulant. The first dielectric layer defines at least one through hole. The conductive element is disposed in the through hole and including a first portion and a second portion. A first surface of the first portion is substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer. The first circuit structure is disposed on the first dielectric layer. The semiconductor die is electrically connected to the first circuit structure. The encapsulant covers the semiconductor die.