Coplanar Control Gate for Semiconductor Memory Cell Miniaturization
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Solution Overview
Problem
The miniaturization of semiconductor memory cells is limited by the need for extra space due to the control gate covering the side surfaces of the floating gate, leading to positional deviations and variations in threshold voltage.
Innovation Solution
A semiconductor device with a control gate and floating gate having coplanar sides, a mono-layered select gate, and a tunnel diffusion layer, where the control gate does not project beyond the floating gate, allowing for space-saving miniaturization and reduced threshold voltage variation, achieved through a manufacturing method involving selective etching and thermal oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control gate covers both front and side surfaces of the floating gate, then the control gate provides complete coverage for electrical control, but extra space is required on the semiconductor substrate leading to limited cell miniaturization
Solution Approach 1:
The patent transitions from a three-dimensional coverage structure (control gate covering front and side surfaces) to a two-dimensional planar structure (control gate coplanar with floating gate sides). This dimensional change eliminates the need for vertical side surface coverage while maintaining electrical control functionality, thereby reducing cell area.
Solution Approach 2:
The patent extracts the side surface coverage function from the control gate structure. By making the control gate coplanar with the floating gate sides rather than extending over them, the side surface coverage is removed, eliminating the associated space requirement and enabling cell miniaturization.
2Area of stationary object
If the side surfaces of the control gate are coplanar with the side surfaces of the floating gate to overcome miniaturization, then cell area is reduced, but alignment accuracy becomes extremely difficult to achieve leading to positional deviation and threshold voltage variation
Solution Approach 1:
The patent merges the formation of the control gate and floating gate into a single simultaneous patterning process. By forming both gates in the same fabrication step using the same mask, the alignment between control gate and floating gate is inherently ensured, eliminating positional deviations and threshold voltage variations while maintaining coplanar geometry for miniaturization.
3Reliability
If a multi-layered control gate structure is used to ensure proper coverage, then electrical control is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent applies local quality by concentrating the control gate's electrical control function at the planar interface with the floating gate rather than distributing it across multiple three-dimensional layers. The coplanar configuration ensures effective electrical control through optimized field distribution at the gate interface, eliminating the need for complex multi-layer structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables miniaturization of memory cells while stabilizing the threshold voltage and eliminating the need for wasteful wiring space, improving the operational stability and efficiency of the memory cells.
Implementation Method 1
a gate insulating film formed on the semiconductor substrate
Implementation Method 2
a tunnel window formed in a portion serving as an electron passage during write/erase operation of data in a gate insulating film
Implementation Method 3
a channel is formed by injecting ions into the base substrate
Data Source
AI summary
A semiconductor device includes a gate insulating film formed on the semiconductor substrate; a floating gate formed on the gate insulating film; a control gate formed on the floating gate and has a side coplanar with a side of the floating gate; a tunnel diffusion layer facing a portion of the floating gate; and a tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window being formed to be thinner than a remaining peripheral portion of the gate insulating film.