Coplanar Semiconductor Die Bandwidth via RDL Interconnect
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Solution Overview
Problem
The fabrication of large-sized semiconductor dies on a wafer suffers from low yield and high cost, necessitating the splitting of dies into smaller ones with identical circuit module designs to improve production yield, while maintaining high bandwidth in chip packaging.
Innovation Solution
A semiconductor chip package design featuring two coplanar dies arranged in a side-by-side fashion with a non-straight line interface gap and a redistribution layer (RDL) structure for electrical connection, which includes a molding compound and a continuous interface gap with segments extending in different directions, enhancing bandwidth by increasing the area for I/O pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large-sized dies are fabricated on a wafer, then the chip can provide sufficient bandwidth, but the production yield is low and cost is high
Solution Approach 1:
The patent divides a large die into multiple smaller dies (first die and second die) that can be fabricated separately on the wafer with higher yield, then connected through RDL structures to achieve the bandwidth equivalent of a single large die. This segmentation allows production of smaller, higher-yield components while maintaining system-level performance.
2Reliability
If large-sized dies are fabricated on a wafer, then the chip can provide sufficient bandwidth, but the manufacturing cost is high
Solution Approach 1:
By segmenting the large die into smaller dies, the patent enables higher production yield and better utilization of wafer real estate, reducing the cost per functional unit. The smaller dies can be manufactured more efficiently and with fewer defects.
3Productivity
If two smaller dies are arranged side-by-side, then production yield is improved, but the bandwidth may be reduced due to smaller individual die size
Solution Approach 1:
The patent uses RDL (redistribution layer) structures that extend in multiple dimensions to create numerous parallel connection paths between the two smaller dies. This multi-dimensional interconnection approach compensates for the reduced size of individual dies by providing abundant I/O pad connections across the interface, thereby maintaining high bandwidth despite the smaller die dimensions.
Data Source
AI summary
A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.