Coplanar Gate Electrodes for HV MV LV Semiconductor Integration
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Solution Overview
Problem
Current semiconductor technology faces challenges in integrating high-voltage, medium-voltage, and low-voltage components on the same device due to differences in transistor formation processes, leading to issues with shallow trench isolation structures and loading effects.
Innovation Solution
A semiconductor device and method that embeds high-voltage and medium-voltage components at the same level as the top surface of low-voltage components, using a substrate with distinct areas for each, ensuring coplanar top surfaces of gate electrodes to simplify processes and avoid depth discrepancies in shallow trench isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-voltage, medium-voltage, and low-voltage components are integrated on the same chip, then cost is reduced and operating efficiency is improved, but differences in transistor formation processes cause shallow trench isolation structures with different depths and serious loading effects
Solution Approach 1:
The chip is divided into distinct high-voltage, medium-voltage, and low-voltage areas with separate transistor formation processes for each region. This segmentation allows each voltage component to be optimized independently while maintaining overall integration, resolving the conflict between integration efficiency and manufacturing precision.
Solution Approach 2:
Different transistor structures are employed in different voltage regions: planar transistors for high-voltage components and FinFETs for low-voltage components. Each region has locally optimized structures and processes tailored to its specific voltage requirements, enabling precise control of isolation depths while maintaining integration.
2Reliability
If different transistor structures (planar and FinFET) are used for high-voltage and low-voltage components, then device performance is optimized, but process complexity increases and integration becomes more difficult
Solution Approach 1:
The device is segmented into separate high-voltage and low-voltage regions, each with its own optimized transistor structure. High-voltage areas use planar transistors while low-voltage areas use FinFETs, allowing each to perform at its optimal level without compromising the other.
Solution Approach 2:
A unified chip design integrates multiple voltage components and transistor types into a single device that can handle both high-voltage and low-voltage operations. The chip serves multiple functions across different voltage domains while maintaining a cohesive structure and process flow.
3Adaptability or versatility
If shallow trench isolation structures are formed with different depths for different voltage components, then each component can be optimized independently, but serious loading effects occur in subsequent processes
Solution Approach 1:
The isolation structures are segmented by voltage region, with each region having isolation depths appropriate to its specific voltage requirements. This segmented approach allows independent optimization of each voltage component while containing the loading effects within localized areas.
Solution Approach 2:
Each voltage region has locally optimized isolation structures with depths tailored to its specific needs. High-voltage regions have deeper isolation while low-voltage regions have shallower isolation, with each locally adapted to minimize loading effects in its specific context.
Data Source
AI summary
A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.