Coplanar Gate eNVM on FD-SOI Substrate
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Solution Overview
Problem
Conventional embedded non-volatile memory (eNVM) devices face challenges due to differing gate heights between NVM cells and logic devices, leading to manufacturing complexity and compatibility issues with silicon-on-insulator (SOI) substrates, particularly with high voltage MOS devices experiencing a floating body effect that impacts performance.
Innovation Solution
The solution involves fabricating semiconductor devices using a crystal-on-insulator (COI) substrate with defined COI and hybrid regions, where NVM transistors are formed in the hybrid region with gates on the bulk substrate and logic transistors in the COI region, ensuring coplanar top surfaces to address gate height differences and floating body effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional eNVM devices are fabricated with different gate heights for NVM cells and logic devices, then device functionality is achieved, but processing complexity increases and manufacturing difficulty worsens
Solution Approach 1:
The patent introduces a vertical dimension solution by forming an extended gate structure that protrudes from the first substrate. This extended gate allows NVM cells and logic devices to have different gate heights on the first substrate while maintaining coplanar top surfaces through the extension into a second substrate, thereby resolving the contradiction between device functionality and manufacturing complexity
Solution Approach 2:
The patent uses a second substrate as an intermediary element to accommodate the extended gate structure. This second substrate acts as a mediator that allows the gate to extend vertically without interfering with the planar integration of NVM cells and logic devices on the first substrate, simplifying the manufacturing process while maintaining device functionality
2Adaptability or versatility
If high voltage MOS devices are integrated on SOI substrates, then device integration is achieved, but floating body effect occurs that negatively impacts device performance
Solution Approach 1:
The patent segments the gate structure into two parts: a first gate portion on the first substrate and a second gate portion extending into the second substrate. This segmentation allows the gate to be electrically isolated from the floating body effect in the SOI substrate while still controlling the channel, thereby improving device performance without sacrificing integration capability
Solution Approach 2:
The patent extracts the gate control function from the conventional planar configuration and extends it vertically into a second substrate. This extraction removes the gate's susceptibility to floating body effects while maintaining its control over the channel, resolving the contradiction between device integration and performance reliability
3Device complexity
If coplanar gate surfaces are formed for NVM and logic devices, then manufacturing ease is improved, but additional processing steps are required to achieve coplanarity
Solution Approach 1:
The patent performs preliminary action by forming the extended gate structure protruding from the first substrate before finalizing the integration of NVM cells and logic devices. This preliminary extension establishes the coplanar top surface configuration early in the manufacturing process, simplifying subsequent processing steps and improving overall manufacturing ease
Data Source
AI summary
A semiconductor device with embedded non-volatile memory (eNVM) is described. The device is formed on a silicon-on-insulator (SOI) substrate, such as a fully depleted SOI (FDSOI) substrate. The substrate includes a SOI region and a hybrid region. The SOI region includes the surface substrate, BOX and bulk substrate while the hybrid region includes only the bulk substrate. NVM and high voltage (HV) transistors are disposed in the hybrid region while a logic and radio frequency (RF) transistors are disposed in the SOI region. The gates of the various transistors have about coplanar top surfaces. As such, the hybrid region compensates for height differential of transistors, enabling transistors to have about coplanar top surfaces. In addition, the hybrid region enables transistors which suffer from floating body effects to be disposed therein.