Coplanar Transmission Line Package Ground Path Brackets Data
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Solution Overview
Problem
Current stripline routing architectures in electronic packaging are ineffective for scaling beyond low memory speeds due to increased crosstalk, which limits the ability to achieve higher memory speeds as silicon processes shrink and the number of memory channels increases.
Innovation Solution
Implementing an end-to-end coplanar routing scheme from the C4 bumps to the package pin, where data traces are bracketed by ground traces, reducing crosstalk and allowing for higher data rates without increasing silicon die area or package layers, and utilizing via offsets and redistributions to accommodate this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stripline routing is used in package, then crosstalk is reduced at low memory speeds, but the routing becomes impracticable for continued scaling to higher memory speeds
Solution Approach 1:
The patent inverts the conventional stripline routing approach by using coplanar routing instead. In stripline routing, the signal travels between two ground planes, while in coplanar routing, the signal and ground traces are on the same plane. This inversion allows the ground path to bracket the data path, providing better control over signal integrity at high speeds while enabling continued scaling to higher memory speeds beyond what stripline routing can achieve.
2Productivity
If coplanar routing with bracketed ground path is implemented, then crosstalk is reduced by 50-70% and data rates increase to 10 GT/s or greater, but the routing complexity increases
Solution Approach 1:
The patent segments the ground path into multiple sections that bracket different portions of the data path. By dividing the ground reference into separate segments along the signal trace, the design achieves better crosstalk reduction and signal integrity control. This segmentation allows the complex high-speed routing to be broken down into manageable sections, each with its own ground bracketing, thereby reducing overall routing complexity while maintaining high data rates of 10 GT/s or greater.
3Reliability
If via offsets and redistributions are used to accommodate coplanar routing, then end-to-end coplanar routing from C4 bumps to package pin is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates via offsets and redistributions as preliminary design features in the routing layer. By pre-planning and pre-positioning the vias with intentional offsets from the pad centers, the design accommodates coplanar routing requirements before the actual signal traces are routed. This preliminary action ensures that ground paths can effectively bracket data paths from C4 bumps to package pin, maintaining signal integrity while managing manufacturing complexity through advance planning rather than post-layout adjustments.
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.