Coplanar Hard Mask Patterns for Fine-Pitch Metal Layer Patterning
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Solution Overview
Problem
The complexity of manufacturing and integration in semiconductor devices leads to deficiencies, necessitating improved processes that can maintain quality while reducing feature size.
Innovation Solution
A semiconductor device structure with coplanar bottom surfaces of hard mask patterns over a metal layer, achieved through a method involving a substrate with a metal layer, hard mask layer, and anti-reflective coating layer, using self-aligned double patterning (SADP) and etching processes to form multiple hard mask patterns with carbon materials, ensuring direct contact with the metal layer and reducing feature size without compromising quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
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If conventional manufacturing processes are used, then manufacturing complexity increases, but feature size reduction capability is limited
Solution Approach 1:
The manufacturing process is segmented into multiple patterning steps (SADP - Self-Aligned Double Patterning) where the hard mask layer is patterned twice to achieve finer features. This breaks down the complex task of creating small features into manageable sequential steps, reducing the overall manufacturing complexity while enabling feature size reduction
Solution Approach 2:
A preliminary hard mask pattern is formed first, then used as a template for creating the final fine-pitch patterns. This preliminary structure guides subsequent etching steps, making the complex feature size reduction achievable through staged processing rather than attempting to create final patterns in a single step
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If feature size is reduced, then device functionality improves, but manufacturing precision requirements increase
Solution Approach 1:
The self-aligned double patterning process uses the previously formed hard mask structures to automatically define the positions of subsequent patterns. The etching process self-aligns to the existing features, eliminating the need for additional alignment operations and maintaining high precision without increasing manufacturing complexity
Solution Approach 2:
Multiple patterning operations are merged into a self-aligned process where the first pattern serves as the alignment reference for the second pattern. This combines positioning and pattern formation into a single integrated process step, achieving high precision while simplifying the overall manufacturing flow
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If multiple patterning steps are implemented, then feature size is reduced, but process complexity increases
Solution Approach 1:
The patterning process is segmented into distinct stages: forming the first hard mask pattern, depositing spacers, removing the first pattern, and forming the second pattern. This segmentation allows each step to be optimized independently while maintaining overall process control, reducing the burden of complexity at any single stage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reduced feature size in semiconductor devices without sacrificing quality, improving manufacturing efficiency and addressing integration complexities by forming coplanar hard mask patterns using SADP and etching processes.
Implementation Method 1
etching the hard mask layer by using the first spacer and the second spacer as a mask to form a first hard mask pattern and a second hard mask pattern
Implementation Method 2
The hard mask layer of the substrate is formed by a plasma enhanced chemical vapor deposition (PECVD) process
Data Source
AI summary
A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.