Semiconductor Structure with Coplanar III-V Devices on Silicon
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Solution Overview
Problem
The integration of silicon and column III-V circuits on separate chips with wire bonds is costly, limits integration complexity, increases footprint, and introduces parasitic resistances and inductances, while existing structures with InP MHEMT on silicon substrates face issues of non-co-planarity, increased thermal resistance, and potential degradation of CMOS and GaN HEMT processes.
Innovation Solution
A semiconductor structure with a silicon substrate of specific crystallographic orientation, featuring a non-nitride column III-V or column II-VI device grown directly on the substrate, eliminating the need for tilted silicon layers and high-temperature anneals, and ensuring coplanarity with silicon CMOS and GaN HEMT surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If InP MHEMT is formed on a silicon layer with tilted orientation to improve III-V material growth, then the growth quality is improved, but the device surface becomes non-co-planar with CMOS surfaces and processing complexity increases
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the silicon substrate from tilted (e.g., <110>) to a specific un-tilted orientation (e.g., <100>). This parameter change eliminates the need for tilted growth layers while maintaining good III-V material growth quality, thereby achieving co-planar device surfaces and simplifying processing.
Solution Approach 2:
Instead of tilting the silicon layer to improve III-V growth (conventional approach), the patent inverts the approach by using an un-tilted silicon substrate with specific orientation that naturally supports high-quality III-V growth without tilting, thus achieving co-planarity and simplified processing.
2Reliability
If InP MHEMT is formed on a silicon layer with insulating oxide to improve electrical isolation, then electrical isolation is improved, but thermal resistance increases and heat dissipation is degraded
Solution Approach 1:
The patent segments the substrate into different functional regions: a first region for CMOS devices with electrical isolation requirements (using insulating oxide), and a second region for InP MHEMT devices where direct substrate contact provides low thermal resistance. This spatial segmentation allows both electrical isolation and thermal management requirements to be satisfied simultaneously.
Solution Approach 2:
The patent applies different structural configurations to different locations: CMOS transistors use the silicon layer with insulating oxide for electrical isolation, while InP MHEMT devices are formed directly on the silicon substrate without the insulating oxide layer to ensure low thermal resistance and efficient heat dissipation.
3Reliability
If silicon and column III-V circuits are fabricated on separate chips with wire bonds to maintain process compatibility, then process compatibility is maintained, but integration complexity increases and parasitic resistances are introduced
Solution Approach 1:
The patent merges silicon CMOS circuit fabrication and InP MHEMT device formation into a single integrated structure on one silicon substrate. Both device types are formed using compatible processing steps performed sequentially on the same substrate, eliminating the need for separate chips and wire bonds, thereby reducing integration complexity and parasitic resistances while maintaining process compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal resistance, simplifies device processing, maintains CMOS process integrity, and enhances the growth of III-V materials by ensuring coplanarity and natural bilayer steps, thereby improving overall circuit performance and integration complexity.
Implementation Method 1
a non-nitride column III-V or column II-VI semiconductor layer having the same crystallographic orientation as the silicon substrate, the non-nitride column III-V or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate
Data Source
AI summary
A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.