Coplanar Interposer Segmentation for Warpage Control
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Solution Overview
Problem
The existing semiconductor packaging technologies face challenges with large-size silicon interposers, which result in decreased yields and increased costs due to warpage during the reflow process, especially when mounting multiple chips like GPUs and HBM chips, as they require larger substrates that are prone to significant warpage.
Innovation Solution
The use of multiple coplanar interposers with a redistribution layer (RDL) structure and different molding compounds to electrically connect and encapsulate dies, allowing for smaller interposer sizes and improved warpage resistance, with the RDL structure including bridge traces to connect the interposers and fill the gap between them with a second molding compound.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a large-size interposer substrate is used to mount multiple chips (GPU and HBM chips), then the surface area requirement is met, but the yield decreases and fabrication cost increases due to warpage during reflow process
Solution Approach 1:
The patent divides a single large interposer substrate into multiple smaller interposer substrates (first interposer substrate, second interposer substrate, etc.). Each smaller substrate is mounted on the package separately, reducing individual substrate warpage while collectively providing the required total surface area for mounting multiple chips.
2Area of stationary object
If a large-size interposer substrate is used to mount multiple chips, then the surface area requirement is met, but the fabrication cost increases due to decreased yield
Solution Approach 1:
By segmenting the large interposer into multiple smaller interposers, each smaller unit can be manufactured with higher yield. The smaller size reduces the probability of defects during fabrication, thereby lowering the cost per interposer while still achieving the required total mounting area through parallel arrangement.
3Area of stationary object
If a large-size interposer substrate is used, then the surface area for mounting multiple chips is sufficient, but significant warpage occurs during reflow process
Solution Approach 1:
The large interposer is divided into multiple smaller interposer substrates. Each smaller substrate experiences less thermal stress and dimensional change during reflow, significantly reducing warpage. The multiple small interposers are arranged in a coplanar configuration to collectively provide the required surface area.
Solution Approach 2:
Different regions of the package are assigned different interposer substrates with optimized local characteristics. Each local interposer is sized appropriately for its specific mounting requirements, allowing better control of warpage in each local region while maintaining overall package functionality.
4Reliability
If multiple coplanar interposers are used instead of a single large interposer, then warpage is reduced and yield is enhanced, but the device complexity increases
Solution Approach 1:
The interposer system is segmented into multiple independent but coplanar substrates. This segmentation reduces warpage and improves yield while the coplanar arrangement and standardized mounting procedures keep the operational complexity manageable.
Solution Approach 2:
Multiple interposer substrates are merged into a coplanar configuration that functions as a unified mounting platform. The bridge traces electrically connect the interposers, creating an integrated system that behaves similarly to a single large interposer while avoiding its warpage problems.
5Shape
If multiple coplanar interposers are used, then smaller interposer sizes are achieved with improved warpage resistance, but additional RDL structure with bridge traces is required to maintain electrical connectivity
Solution Approach 1:
Bridge traces act as intermediary conductors that electrically connect adjacent interposer substrates. These traces are integrated into the RDL structure, providing a straightforward method to maintain electrical connectivity across multiple interposers without requiring complex wiring solutions.
Data Source
AI summary
A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.