Coplanar Lead Semiconductor Package Without Punching or Bending

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Solution Overview

Problem

Conventional semiconductor package manufacturing involves costly and complex processes such as molding, lead frame punching, trimming, and lead bending, which can lead to stress accumulation in leads and inefficiencies in encapsulant application.

Innovation Solution

A flat semiconductor package design with coplanar leads, where an encapsulant layer comprehensively covers the lead frame and leads, eliminating the need for mechanical processing steps like punching and bending, and allowing for a flat, stress-reduced configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional molding, punching, and lead bending processes are used, then semiconductor packages can be manufactured with specific shapes, but manufacturing cost increases and lead stress accumulates

Engineering Contradiction:
Improvelead reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the harmful mechanical processing steps (punching, lead bending, trimming) from the manufacturing process. By taking out these complex mechanical operations, the lead frame is directly formed with the final coplanar lead configuration, preventing stress accumulation and simplifying the overall manufacturing process while maintaining product reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of forming leads through mechanical deformation (bending) after molding, the patent inverts the approach by directly forming the lead frame with coplanar leads in the desired final configuration before molding. This inversion eliminates the need for subsequent lead bending operations and reduces manufacturing complexity

Inventive Principle:
Principle #13The other way round (Inversion)

2Ease of manufacture

If multiple punching and lead bending machines are used, then leads can be formed in specific shapes, but equipment cost increases

Engineering Contradiction:
Improvelead formation easeVSAvoidequipment complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single lead frame structure that can be directly molded into the final coplanar lead configuration without requiring multiple specialized machines. The lead frame serves multiple functions: it provides structural support, electrical connectivity, and the final lead shape, eliminating the need for separate punching and bending equipment

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent replaces mechanical lead formation processes (punching, bending) with a molding process that directly forms the lead frame in its final configuration. This substitution eliminates the need for mechanical processing equipment and reduces overall device complexity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Manufacturing precision

If conventional molding process is used, then chips can be embedded in encapsulant, but residual encapsulant remains requiring additional trimming

Engineering Contradiction:
Improveencapsulant application precisionVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by designing the mold cavity and lead frame configuration to work together in advance, ensuring that the encapsulant is precisely contained during molding. The coplanar lead configuration and mold design are pre-coordinated to prevent encapsulant overflow, eliminating the need for subsequent trimming operations and improving manufacturing efficiency

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250112130A1Flat semiconductor package with coplanar leads
Publication Date: 2025.04.03 PANJIT INT INC
  • US20250112130A1 patent drawing
  • US20250112130A1 patent drawing
  • US20250112130A1 patent drawing

AI summary

A flat semiconductor package includes a die pad, a die attached on the die pad, multiple leads distributed around the die pad and electrically connected to the die, and an encapsulant layer covering the die pad, the die and the leads. The encapsulant layer has a flat cuboid configuration having side surfaces from which the multiple leads laterally extend without being bent. Bottom surfaces of the die pad, the multiple leads and the encapsulant layer are coplanar. Manufacturing of the flat semiconductor package prevents the use of specific machines for encapsulant molding, punching and lead bending. When the leads are soldered onto a circuit board, more solder adhere on each lead laterally extending from the flat semiconductor package. Further, the stress accumulated on the leads is less and the reliability of the flat semiconductor package can be improved.