Coplanar Multi-Chip Molding Structure for Low-Warpage Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to warpage issues in chip package structures caused by varying coefficients of thermal expansion.
Innovation Solution
The process involves using a carrier substrate with a lower coefficient of thermal expansion than the molding layer to reduce warpage, forming adhesive and molding layers with specific materials, and performing debonding and sawing processes to create individual chip package structures while maintaining coplanarity of surfaces, thereby improving yield and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple stages: forming recesses in the substrate, depositing first interconnection structures, forming second interconnection structures in subsequent recesses, and creating via holes to connect them. This segmentation allows complex 3D integration to be achieved through manageable sequential steps, resolving the contradiction between increased functionality and manageable process complexity
2Stability of the object's composition
If carrier substrate with lower coefficient of thermal expansion is used, then warpage is reduced, but material selection constraints increase
Solution Approach 1:
The patent specifies that the carrier substrate must have a lower coefficient of thermal expansion than the molding layer to compensate for thermal expansion differences during curing and operation. This parameter control prevents warpage by ensuring the substrate contracts less than the molding layer when cooled, maintaining planarity despite reduced material selection flexibility
3Strength
If adhesive layer is formed between carrier substrate and molding layer, then bonding strength increases, but process steps increase
Solution Approach 1:
The adhesive layer is applied to the carrier substrate before the molding layer is formed, creating a pre-prepared bonding interface. This preliminary action ensures strong adhesion between the molding layer and substrate while organizing the process flow efficiently, as the adhesive is already in place when the molding layer is deposited
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage in chip package structures, enhances yield, and lowers production costs by optimizing material selection and processing steps, resulting in more efficient and reliable chip package formation.
Implementation Method 1
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to warpage issues in chip package structures caused by varying coefficients of thermal expansion
Implementation Method 2
forming adhesive and molding layers with specific materials
Data Source
AI summary
A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.