Coplanar Oxide TFT UV Conductive Areas
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Solution Overview
Problem
The manufacturing of coplanar type oxide thin film transistors (TFTs) faces issues such as short circuit defects and step coverage problems due to the dry etching process used for the gate insulation layer, which can damage the buffer layer and lead to reliability degradation.
Innovation Solution
A method involving a semiconductor layer with an oxide semiconductor on a buffer, covered by a gate insulation layer and a passivation layer, where ultraviolet (UV) irradiation is used to create conductive areas without etching the gate insulation layer, forming conductors with different resistances for the first and second electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate insulation layer is etched through a dry etching process to form the first electrode and second electrode, then the electrodes can be formed, but the buffer layer is damaged and step height occurs causing short circuit defects
Solution Approach 1:
The patent extracts the gate insulation layer etching step from the manufacturing process. Instead of etching the gate insulation layer to form electrodes, the invention uses a different approach where the gate electrode is formed first, then the gate insulation layer is deposited to cover it, eliminating the need for etching and preventing buffer layer damage
Solution Approach 2:
The patent inverts the conventional sequence of operations. Instead of forming electrodes by etching the gate insulation layer (conventional approach), the invention forms the gate electrode first, then deposits the gate insulation layer over it (inverted approach), thereby avoiding etching-related damage to the buffer layer
2Ease of manufacture
If the gate insulation layer is over-etched during the dry etching process, then the electrode formation is completed, but the buffer layer is damaged or removed
Solution Approach 1:
The patent applies preliminary anti-action by preventing the etching process from occurring in the first place. The gate electrode is formed before the gate insulation layer is deposited, so there is no need for subsequent etching that could cause over-etching and buffer layer damage
Solution Approach 2:
The patent provides beforehand cushioning by forming the gate electrode structure before depositing the gate insulation layer. This sequence ensures that the buffer layer is protected from etching damage, as the gate electrode serves as a protective structure during the deposition process
3Productivity
If the gate insulation layer and buffer layer are over-etched, then the electrode formation is achieved, but the light shielding layer is exposed or buffer thickness is reduced causing short circuit
Solution Approach 1:
The patent performs preliminary action by forming the gate electrode before depositing the gate insulation layer. This preliminary structuring eliminates the need for etching operations that could expose the light shielding layer or reduce buffer layer thickness, thereby preventing short circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects, enhances device performance by increasing mobility and current, and simplifies the manufacturing process by eliminating the need for dry etching, thereby improving the reliability and characteristics of the oxide TFTs.
Implementation Method 1
ultraviolet (UV) irradiation is used to create conductive areas without etching the gate insulation layer
Data Source
AI summary
Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, and a display panel and a display device using the same, in which a first conductor and a second conductor are provided at end portions of a semiconductor layer formed of oxide semiconductor. The first conductor and second conductor are electrically connected to a first electrode and a second electrode, and covered by a gate insulation layer. The oxide TFT includes a semiconductor layer provided on a buffer and including an oxide semiconductor, a gate insulation layer covering the semiconductor layer and the buffer, a gate electrode provided on the gate insulation layer to overlap a portion of the semiconductor layer, and a passivation layer covering the gate and the gate insulation layer.