Coplanar Pad Architecture Using III-V Cladding Planarization
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Solution Overview
Problem
The fabrication of high-speed optoelectronic components is complicated and time-consuming due to the need for planarization using materials like benzocyclobutene (BCB) or silicon oxynitride (SiON), which introduce parasitic capacitance, thermal instability, and non-uniformity, making it difficult to achieve consistent planarization and electrical integrity.
Innovation Solution
A method involving selective epitaxial growth of a III-V semiconductor cladding layer on a multi-layered wafer, with etching steps to define a slab and ridge, followed by electrical contacts, to achieve improved planarization and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If BCB is used for planarization, then parasitic capacitance is reduced, but the process becomes complex and time-consuming with inconsistent yield
Solution Approach 1:
The patent removes the separate planarization step and BCB material entirely by integrating the cladding layer formation to simultaneously provide both optical confinement and electrical planarization. The cladding layer is grown to extend beyond the ridge sidewalls and contact the slab, eliminating the need for additional planarization materials and processes.
Solution Approach 2:
The patent combines the optical cladding function and electrical planarization function into a single III-V semiconductor cladding layer. This merged structure serves dual purposes: providing optical confinement for the waveguide and creating a planar surface for electrical contacts, thereby simplifying the overall fabrication process.
2Reliability
If BCB is used for planarization, then electrical connectivity is improved, but thermal stability deteriorates
Solution Approach 1:
The patent changes the material parameter from organic polymer (BCB) to inorganic III-V semiconductor material. This parameter change provides both electrical connectivity through the semiconductor material and thermal stability through its inherent resistance to high temperatures, allowing subsequent annealing processes without material degradation.
3Stability of the object's composition
If SiON is used for planarization, then thermal stability is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent employs selective epitaxial growth where the III-V semiconductor cladding layer automatically grows to a uniform height across the substrate, self-regulating the planarization process. The growth stops when the cladding contacts the slab, providing inherent planarization uniformity without requiring precise thickness control or additional etching steps.
4Manufacturing precision
If multiple coating and baking steps are performed for BCB planarization, then planarization is achieved, but production time increases
Solution Approach 1:
The patent extracts and eliminates the multiple coating, baking, and etching steps associated with BCB planarization. Instead, a single selective epitaxial growth step is performed where the cladding layer forms and simultaneously planarizes the surface, reducing the number of process steps and increasing fabrication speed.
5Manufacturing precision
If SiON planarization is performed with thick dielectric growth, then planarization is achieved, but strain management becomes difficult leading to device failure
Solution Approach 1:
The patent changes the dielectric material parameter from SiON to III-V semiconductor material, which has different mechanical properties and strain characteristics. The III-V cladding layer can accommodate the strain from the ridge structure without failure, providing both planarization uniformity and enhanced device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in a more efficient, consistent, and less complex fabrication process with improved planarization and higher yield, reducing the risk of electrical leakage and thermal instability.
Implementation Method 1
selectively epitaxially growing a III-V semiconductor cladding adjacent to a first and second sidewall of the ridge, the cladding layer extending from the upper surface of the slab along the first and second sidewalls
Data Source
AI summary
A method of fabricating an optoelectronic component, performed on a multi-layered wafer disposed on a substrate. The method comprises the steps of: etching the multi-layered wafer, thereby defining a slab and a multi-layered ridge, the slab having an upper surface below the ridge and being located between the multi-layered ridge and the substrate; selectively epitaxially growing a III-V semiconductor cladding adjacent to a first and second sidewall of the ridge, the cladding layer extending from the upper surface of the slab along the first and second sidewalls, and thereby cladding an optically active waveguide within the multi-layered ridge; and providing a first and second electrical contact, which electrically connect to a layer of the multi-layered ridge and the slab respectively.