Coplanar Recessed Gate Layers for Transistor Uniformity
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Solution Overview
Problem
As integration density of transistors increases, existing semiconductor fabrication processes face challenges in maintaining uniform gate structure heights, leading to defects and electrical noise due to height variations in gate and contact structures, which degrade transistor performance.
Innovation Solution
A method involving the fabrication of semiconductor structures with recessed gate layers and gate material, where the upper surfaces of the recessed conformal gate layers and gate material are made coplanar through controlled etching processes, ensuring uniformity and reducing height variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional gate metallization processing is used to deposit conductive material into openings, then the fabrication process can be completed, but height variations in gate structures occur leading to defects and electrical noise
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial gate structure before the final gate metallization. This sacrificial structure serves as a placeholder that defines the gate region and enables subsequent selective recessing of gate layers. The sacrificial gate is formed, then gate dielectric and work function layers are deposited conformally, followed by selective removal of the sacrificial gate material to create the final gate structure with controlled height and uniformity.
Solution Approach 2:
The gate structure is segmented into multiple functional layers: gate dielectric layer, work function layer, and gate metal layer. Each layer can be independently processed and recessed to achieve the desired final configuration. This segmentation allows precise control over each layer's thickness and position, ensuring uniform gate height across the substrate while maintaining reliable transistor performance.
2Productivity
If integration density of transistors is increased, then more transistors can be fabricated on a wafer, but defects and electrical noise increase due to height variations
Solution Approach 1:
The patent employs parameter changes by systematically adjusting the thickness parameters of each gate layer (gate dielectric layer thickness, work function layer thickness, gate metal layer thickness) to achieve uniform gate structure height. By controlling these parameters across the entire wafer through conformal deposition processes, the invention maintains manufacturing precision even as transistor integration density increases, preventing defects and electrical noise.
3Manufacturing precision
If gate layers are recessed to achieve coplanar surfaces, then uniformity is improved, but additional fabrication steps are required
Solution Approach 1:
The sacrificial gate structure is formed in advance as a preliminary structure that guides the subsequent recessing process. This preliminary structure enables selective removal of gate layers only in regions where the sacrificial gate was present, automatically achieving coplanar surfaces without requiring complex additional patterning steps. The preliminary sacrificial gate acts as a mask that simplifies the overall fabrication complexity.
Data Source
AI summary
Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.