Coplanar Semiconductor Package with Slot for Thin Profile
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Solution Overview
Problem
In semiconductor packaging, achieving high-capacity while minimizing thickness and preventing package parasitics, existing technologies face challenges with stacked semiconductor chips, as they tend to increase thickness and suffer from signal skew due to via disposition on the printed circuit board.
Innovation Solution
A semiconductor package design featuring a printed circuit board with a slot, where multiple semiconductor chips are mounted coplanarly, connected via wires and solder balls, and encapsulated with molding layers to prevent delamination and signal skew, utilizing inter-chip and slot molding layers to maintain package thickness and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked to increase capacity, then the package capacity is improved, but the package thickness increases and signal skew occurs due to via disposition
Solution Approach 1:
The patent transitions from vertical stacking (3D stacking increasing thickness) to coplanar arrangement (2D layout maintaining thin profile). Multiple semiconductor chips are mounted side-by-side on the same plane of the printed circuit board, covering different portions of a slot, thereby increasing package capacity without increasing package thickness.
Solution Approach 2:
The printed circuit board includes a slot that is divided into multiple portions, with each semiconductor chip mounted to cover a different portion of the slot. This segmentation allows multiple chips to be arranged coplanarly while maintaining electrical connectivity through the slot structure, resolving the contradiction between capacity and thickness.
2Reliability
If via disposition is used for electrical connection, then electrical connectivity is achieved, but signal skew occurs
Solution Approach 1:
The patent extracts the electrical connection path from the traditional via disposition method and replaces it with wire connections that route signals along the slot. This eliminates the signal skew caused by via disposition while maintaining electrical connectivity between the coplanarly arranged chips.
Solution Approach 2:
The slot structure serves as an intermediary element that facilitates electrical connection between coplanarly arranged chips without requiring vertical vias. Wires routed through or along the slot provide signal transmission paths that avoid the signal skew issues associated with traditional via dispositions.
3Quantity of substance
If multiple chips are mounted to cover different portions of the slot, then package capacity increases, but delamination risk increases
Solution Approach 1:
The patent merges multiple semiconductor chips and the slot structure into a unified coplanar assembly. By arranging chips to cover different portions of the slot on the same plane and using wire connections routed through the slot, the design increases capacity while maintaining package integrity and preventing delamination through unified structural support.
Data Source
AI summary
The semiconductor package includes a printed circuit board, a first semiconductor chip, and a second semiconductor chip. The printed circuit board includes a slot. The first semiconductor chip is mounted on the printed circuit board to cover a first part of the slot. The second semiconductor chip is mounted on the printed circuit board to cover a second part of the slot separate from the first part. The first semiconductor chip is substantially coplanar with the second semiconductor chip.