Coplanar Semiconductor Connection Pad via Single Plating
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Solution Overview
Problem
Conventional semiconductor packages face challenges in reducing the thickness and improving the performance due to protruding connection pads that leave residue from tape used during stacking, and the complexity of forming vias and connection pads using separate processes.
Innovation Solution
A semiconductor device design where the top surface of the upper insulating layer on a non-active surface of the semiconductor chip is coplanar with the connection pad, and both the via and connection pad are formed using a single plating process, eliminating protrusion and simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection pads are formed to protrude above the upper insulating layer for electrical connection, then electrical connection is achieved, but tape residue remains on the protruding pads during stacking
Solution Approach 1:
The patent applies the 'Blessing in disguise' principle by converting the harmful effect of tape residue into a beneficial design feature. Instead of allowing tape contact with protruding pads (which causes residue), the connection pads are designed to be coplanar with the upper insulating layer surface. This allows the tape to pass over without leaving residue, while electrical connection is still achieved through the coplanar pad structure combined with via connections.
2Reliability
If connection pads are formed to protrude above the upper insulating layer, then electrical connection is achieved, but package thickness increases
Solution Approach 1:
The patent applies the 'Another dimension' principle by transitioning from a vertical protrusion design to a coplanar horizontal design. Instead of extending connection pads in the vertical dimension (protruding above the insulating layer), the pads are positioned in the same plane as the insulating layer surface, achieving electrical connection through lateral extension and via connections rather than vertical protrusion.
3Manufacturing precision
If vias and connection pads are formed using separate processes, then manufacturing precision is maintained, but manufacturing complexity and time increase
Solution Approach 1:
The patent applies the 'Merging' principle by combining the via formation and connection pad formation into a single plating process. The method involves forming via holes, applying a barrier metal layer to the via walls, and then performing a single plating operation that simultaneously forms both the via fill and the connection pads. This integrated approach reduces manufacturing steps while maintaining precision through controlled plating parameters.
4Manufacturing precision
If multiple separate processes are used to form vias and connection pads, then manufacturing precision is maintained, but production time increases
Solution Approach 1:
The patent applies the 'Continuity of useful action' principle by implementing a continuous plating process that forms both vias and connection pads in one uninterrupted operation. The plating is performed continuously after barrier metal deposition, eliminating the need for separate plating steps for vias and pads. This continuous process maintains precision through consistent plating conditions while significantly reducing total manufacturing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the thickness of semiconductor packages by preventing tape residue on connection pads and streamlines the manufacturing process, enhancing performance and cost-effectiveness.
Implementation Method 1
both the via and connection pad are formed using a single plating process
Data Source
AI summary
A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.