Semiconductor Package Side Surface Protector for Singulation Reliability
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Solution Overview
Problem
The reliability of side surfaces in semiconductor packages is compromised due to cracks and unevenness resulting from the singulation process, which can lead to increased susceptibility to external forces and potential damage.
Innovation Solution
A semiconductor package design that incorporates a side surface protector extending from the insulating layer of the rewiring structure, ensuring coplanarity with the semiconductor device's surfaces and formed using the same material as the insulating layer, thereby preventing direct exposure and reducing the occurrence of cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a singulation process is performed to individualize semiconductor packages, then the semiconductor substrate is divided into separate devices, but cracks and unevenness are generated on the side surfaces
Solution Approach 1:
The side surface protector is formed on the side surfaces of the semiconductor substrate before the singulation process. This preliminary protective action prevents cracks and unevenness from occurring during the subsequent singulation cutting process, thereby maintaining side surface integrity while enabling efficient individualization of semiconductor packages.
Solution Approach 2:
The side surface protector acts as a cushioning layer that absorbs and distributes the mechanical stress and forces applied during the singulation process. By providing this beforehand cushioning, the protector prevents the generation of cracks and reduces surface unevenness on the semiconductor substrate sides.
2Reliability
If the side surface protector extends beyond the semiconductor device to cover the rewiring structure, then protection against external forces is improved, but the structure becomes more complex
Solution Approach 1:
The side surface protector serves multiple functions: it protects the semiconductor device side surfaces from cracks during singulation, covers and protects the rewiring structure from external forces and moisture, and provides a planar upper surface for subsequent packaging processes. By consolidating these multiple protective functions into a single structure, the design achieves enhanced reliability without proportionally increasing complexity.
Solution Approach 2:
The side surface protector is integrated with the insulating layer of the rewiring structure, forming a unified protective system. This merging of the protector with existing package structures reduces the need for separate components and simplifies the overall manufacturing process while maintaining comprehensive protection.
3Ease of manufacture
If the upper surface of the side surface protector is coplanar with the semiconductor device surface, then subsequent packaging processes are facilitated, but the protector must extend beyond the device edges
Solution Approach 1:
The side surface protector exhibits different geometric characteristics at different locations: the upper surface is coplanar with the semiconductor device to facilitate subsequent packaging processes, while the sides extend beyond the device edges to provide comprehensive protection. This local differentiation of geometric quality optimizes both manufacturing ease and protective function.
Data Source
AI summary
Provided is a semiconductor package including a rewiring structure including a rewiring pattern, and at least one insulating layer, a semiconductor device provided on the rewiring structure, and electrically connected to the rewiring pattern, and a side surface protector covering a first side surface of the semiconductor device, wherein an upper surface of the semiconductor device that is opposite to a lower surface of the semiconductor device facing the rewiring structure and an upper surface of the side surface protector are at the same vertical level and are coplanar with each other, and the side surface protector extends from the insulating layer of the rewiring structure.


