Coplanar Test Patterns for Through-Wafer Via Misalignment Detection
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Solution Overview
Problem
Current methods lack effective alignment techniques for through-wafer vias (TWVs) in the via-last approach, leading to misalignment issues that are only detectable at the wafer-sorting stage, resulting in circuit failure and requiring destructive testing methods like TEM or SEM.
Innovation Solution
A semiconductor chip design incorporating a test pattern with coplanar conductive patterns and a through-wafer via, allowing for early detection of misalignment without damaging the wafer, by forming central and surrounding conductive patterns that are electrically connected to bonding pads, enabling non-destructive assessment of TWV alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If through-wafer vias are formed using the via-last approach without alignment methods, then manufacturing flexibility is improved, but manufacturing precision deteriorates due to TWV misalignment
Solution Approach 1:
The patent applies preliminary action by forming test patterns (conductive patterns with bonding pads) before through-wafer via formation. These test patterns serve as alignment references that enable detection and correction of TWV misalignment before actual device fabrication, thus maintaining manufacturing flexibility while improving alignment precision.
2Device complexity
If misalignment is detected only at wafer-sorting stage, then manufacturing process simplicity is maintained, but productivity deteriorates due to yield loss
Solution Approach 1:
The patent implements preliminary detection by incorporating test patterns that enable misalignment detection at the wafer fabrication stage rather than waiting for wafer-sorting. This early detection allows for process adjustments that prevent yield loss, improving productivity while maintaining reasonable process simplicity.
Solution Approach 2:
The test patterns are self-contained structures with bonding pads that enable automatic electrical continuity testing. The system uses its own built-in test patterns to detect misalignment, eliminating the need for external destructive analysis methods and enabling rapid, non-destructive detection that preserves productivity.
3Measurement precision
If conventional TEM or SEM methods are used to analyze misaligned wafers, then measurement precision is improved, but the wafer is damaged
Solution Approach 1:
The patent employs electrical continuity testing through bonding pads as a self-diagnostic mechanism. The test patterns include conductive paths that allow electrical measurement of TWV alignment without requiring physical sectioning or destructive microscopy. This non-destructive method maintains wafer integrity while providing sufficient precision for alignment detection.
Solution Approach 2:
The patent replaces mechanical/destructive analysis methods (TEM, SEM requiring physical sectioning) with an electrical testing approach. By using electrical continuity measurements through the conductive patterns and bonding pads, the system achieves misalignment detection without mechanical damage to the wafer structure.
4Stability of the object's composition
If wafer thickness is significantly greater than circuit dimensions, then structural stability is improved, but manufacturing precision deteriorates due to TWV tilting causing top surface deviation
Solution Approach 1:
The patent applies preliminary action by forming test patterns at the wafer top surface before TWV formation. These test patterns include bonding pads positioned to detect TWV top surface location. By establishing these reference points beforehand, the system can detect and correct TWV tilting-induced position deviations while maintaining the structural stability provided by thick wafers.
Data Source
AI summary
A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns.