Small-gap coplanar tunable capacitors with sidewall spacers
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Solution Overview
Problem
Current tunable capacitors face challenges in achieving optimal power handling and linearity due to the need for multiple long thin bias lines, which can lead to electrostrictive resonance and high tuning voltages, making them less efficient for high-frequency applications.
Innovation Solution
A coplanar tunable capacitor design incorporating sidewall spacers and a voltage-tunable dielectric layer, where the sidewall spacers define the dielectric thickness and separate the bias lines from the RF electrode, reducing electrostrictive resonance and tuning voltage, and allowing for the use of high-K ferroelectric materials like BST.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple long thin bias lines are used in current tunable capacitors, then capacitance tuning capability is achieved, but electrostrictive resonance and high tuning voltages occur
Solution Approach 1:
The capacitor structure is segmented into distinct regions with separate bias lines and RF electrodes, where sidewall spacers create isolated capacitor regions. This segmentation prevents the formation of long continuous bias lines that cause electrostrictive resonance, while maintaining capacitance tuning capability through localized electric field control in each segmented region.
Solution Approach 2:
Sidewall spacers are introduced as intermediary structures between the bias lines and RF electrodes. These spacers serve as mediators that define the capacitor gap and control the electric field distribution, enabling capacitance tuning without requiring long thin bias lines that generate electrostrictive resonance.
2Adaptability or versatility
If multiple long thin bias lines are used in current tunable capacitors, then capacitance tuning capability is achieved, but high tuning voltages are required
Solution Approach 1:
The capacitor structure is segmented into distinct regions with separate bias lines and RF electrodes, where sidewall spacers create isolated capacitor regions. This segmentation prevents the formation of long continuous bias lines that cause electrostrictive resonance, while maintaining capacitance tuning capability through localized electric field control in each segmented region.
Solution Approach 2:
The patent transitions from a planar configuration to a three-dimensional structure using sidewall spacers that extend vertically. This dimensional change allows the bias lines to be separated from the RF electrodes in the vertical dimension, reducing the required tuning voltage while maintaining capacitance control through the spacer-defined gap.
3Manufacturing precision
If deep-submicron lithography is used to achieve small gaps, then manufacturing precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
Sidewall spacers are introduced as intermediary structures between the bias lines and RF electrodes. These spacers serve as mediators that define the capacitor gap and control the electric field distribution, enabling capacitance tuning without requiring long thin bias lines that generate electrostrictive resonance.
Solution Approach 2:
The patent changes the manufacturing approach by using sidewall spacer deposition and etching processes instead of direct lithographic patterning for gap definition. This parameter change in the manufacturing process allows gap precision to be achieved through conformal film deposition and anisotropic etching rather than requiring deep-submicron lithography, reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the Q factor, reduces tuning voltage, and improves capacitance, enabling efficient operation at high frequencies without the need for deep-submicron lithography, while maintaining low leakage and flexibility in capacitor design.
Implementation Method 1
A voltage-tunable dielectric layer is disposed over the substrate
Implementation Method 2
Tunable capacitors have various uses in RF systems including as voltage-tunable devices
Implementation Method 3
allowing for the use of high-K ferroelectric materials like BST
Data Source
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AI summary
A coplanar capacitor that include: a substrate (103); a voltage-tunable dielectric layer (107) over the substrate (103); a plurality of bias lines (109A, 109B,...) over the voltage-tunable dielectric layer (107) wherein the bias lines (109A, 109b,...) are covered by an inter-level dielectric (111A, 111B,..); a plurality of sidewall spacers ( 113A, 113B, 113C, 113D, ... ) wherein each of the sidewall spacers ( 113A, 113B, 113C, 113D, ... ) is located adjacent one of the bias lines (109A, 109B,...) and each of the sidewall spacers (113A, 113B, 113C, 113D, ... ) spans between a respective portion of the voltage-tunable dielectric layer (107) and a respective portion of the inter-level dielectric (111A, 111B,..);; and an electrode (115) over the inter-level dielectric (111A, 111B,..), and over portions of the voltage-tunable dielectric layer (107) that are not covered by the plurality of bias lines (109A, 109B,...) and that are not covered by the sidewall spacers (113A, 113B, 113C, 113D, ... ), wherein a plurality of gaps (117A, 117B) are disposed in the electrode(115).