Package-on-Package IC Packaging with Coplanar Vertical Connectors
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in achieving miniaturization, increased density, and cost reduction while maintaining reliability and performance, particularly in portable electronic devices, as existing solutions do not adequately address the need for space savings and low-cost manufacturing.
Innovation Solution
The development of an integrated circuit packaging system that includes a peripheral lead with an interior conductive layer and a vertical connector, where the integrated circuit is connected to the conductive layer and encapsulated with a coplanar encapsulation top side, allowing for a stackable and routable design that eliminates the need for laser ablation and ball attach processes, reducing substrate costs and improving structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional packaging processes are used, then manufacturing is simpler, but space utilization is poor and cost is high
Solution Approach 1:
The patent transitions from traditional planar packaging to a three-dimensional stacked architecture where multiple integrated circuits are vertically arranged and interconnected through through-substrate vias. This dimensional change enables significantly improved space utilization by stacking components in the vertical direction rather than spreading them out horizontally, directly addressing the space constraints in portable devices.
Solution Approach 2:
The patent implements a nested structure where one integrated circuit package is positioned within or adjacent to another package structure, with through-substrate vias penetrating through multiple layers to establish interconnections. This nesting approach allows multiple functional layers to be compactly arranged, maximizing space efficiency while maintaining electrical connectivity between stacked components.
2Quantity of substance
If more integrated circuits are integrated into a single package, then density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the packaging system into discrete, modular segments - individual integrated circuits are separately packaged with their own substrate and connection structures, then stacked and interconnected. This segmentation allows each module to be manufactured independently using standardized processes, reducing overall manufacturing complexity despite high density, as modules can be produced in parallel and assembled through systematic stacking.
Solution Approach 2:
The patent employs universal substrate structures and standardized through-substrate via configurations that can be replicated across multiple integrated circuits. This multi-functionality approach allows the same manufacturing processes and structural elements to serve multiple purposes across different package layers, simplifying production while achieving high circuit density through repeated modular units.
3Volume of moving object
If package size is reduced for miniaturization, then portability improves, but manufacturing precision requirements increase
Solution Approach 1:
By stacking packages vertically in the third dimension, the patent reduces the horizontal footprint and overall package volume suitable for portable devices. The through-substrate via structure provides precise vertical alignment references that maintain manufacturing precision requirements at acceptable levels despite miniaturization, as the via holes serve as self-aligning features for inter-layer connections.
Solution Approach 2:
The through-substrate vias act as intermediary alignment features between stacked package layers. These vias provide precise mechanical and electrical registration points that facilitate accurate positioning of upper packages relative to lower ones, thereby maintaining manufacturing precision during assembly even as overall package dimensions are reduced for portability.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side.