Coplanar Waveguide Shielding Layer With Interdigitated Fingers

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Solution Overview

Problem

Traditional coplanar waveguide circuits in high-frequency designs consume valuable routing area due to signal return lines, limiting the number of interconnections available in complex integrated circuits, especially in mobile RF devices.

Innovation Solution

Integration of a shielding layer with interdigitated conductive fingers forming a metal-oxide-metal (MOM) capacitor within the coplanar waveguide structure, which repurposes unused shielding area to store capacitance while maintaining signal integrity at RF frequencies and isolating at lower frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If signal return lines are used in traditional coplanar waveguide circuits, then signal integrity is maintained, but routing area is consumed and the number of available interconnections is reduced

Engineering Contradiction:
Improvesignal integrityVSAvoidrouting area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves the signal return path from the same plane (2D coplanar arrangement) to a different interconnect level (3D vertical arrangement). The ground plane is placed on a lower interconnect level beneath the signal line, allowing the signal return path to exist in a different dimensional plane. This eliminates the need for coplanar ground strips adjacent to the signal line, freeing up routing area while maintaining signal integrity through the vertical ground-signal-ground structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The lower interconnect level serves multiple functions: it provides the ground plane for signal return paths (electrical function) and simultaneously acts as a routing layer for additional signal interconnections (interconnection function). By making the lower interconnect level universal for both grounding and signaling purposes, the design maximizes the number of available interconnections while ensuring signal integrity through the ground plane.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If more interconnect layers are added to support increased number of devices, then device interconnection capability is improved, but manufacturing complexity and routing area consumption increase

Engineering Contradiction:
Improvedevice interconnection capabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the interconnect structure into distinct functional segments: upper interconnect levels dedicated to signal routing and a lower interconnect level dedicated to grounding and additional signaling. This segmentation allows each layer to be optimized independently - the lower level provides a continuous ground plane that simplifies manufacturing compared to patterned ground strips, while upper levels handle signal routing. The modular segmentation reduces overall manufacturing complexity despite supporting multiple devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By transitioning from 2D coplanar interconnection to 3D multi-level interconnection, the patent enables increased device interconnection capability without proportionally increasing routing area consumption. The vertical stacking of interconnect levels allows signals to route above and below ground planes, effectively multiplying the interconnection capacity within the same footprint while maintaining manageable manufacturing complexity through standardized layer structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases capacitive density and reduces area occupancy by the signal line, allowing for more efficient use of space in integrated circuits while maintaining effective signal shielding and transmission.

Implementation Method 1

The first ground plane, the second ground plane, the dielectric layer, and the shielding layer may form a capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

Only a dielectric layer may be between the first set of conductive interdigitated fingers and the second set of conductive interdigitated fingers

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS10446898B2On-chip coplanar waveguide having a shielding layer comprising a capacitor formed by sets of interdigitated fingers
Publication Date: 2019.10.15 QUALCOMM INC
  • US10446898B2 patent drawing
  • US10446898B2 patent drawing
  • US10446898B2 patent drawing

AI summary

A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The coplanar waveguide may further include a shielding layer at a second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers that are coupled to the second ground plane. Only a dielectric layer may be between the first set of conductive interdigitated fingers and the second set of conductive interdigitated fingers. The first ground plane, the second ground plane, the dielectric layer, and the shielding layer may form a capacitor.