Self-Assembly Copolymer Narrowing Gate Spacing in Semiconductor Manufacturing
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in reducing the distance between neighboring electrically isolated gates to achieve higher integration density, particularly in the Line-and-Cut dual patterning process, which results in defects such as hallows and short-circuits due to the narrow cuts required for sidewall spacers.
Innovation Solution
A method involving the formation of self-assembly copolymers within openings to narrow the distance between gate lines, followed by ion implantation to create insulating regions without physically cutting the gate lines, allowing for reduced spacing between gates and preventing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between ends of neighboring gates is reduced to increase integration density, then integration density is improved, but manufacturing precision becomes increasingly difficult to achieve
Solution Approach 1:
The photoresist layer performs self-assembly to form openings with precise spacing without requiring external intervention for positioning. The self-organizing behavior of the photoresist molecules during deposition and patterning automatically achieves the required precision for narrow gate spacing, eliminating the need for complex alignment procedures that would be needed at smaller dimensions.
Solution Approach 2:
The gate lines are formed first, and then the photoresist layer is deposited and patterned to form openings relative to these pre-formed gates. This preliminary formation of gate lines provides a stable reference structure that simplifies subsequent patterning steps and maintains precision even as gate spacing is reduced.
2Quantity of substance
If narrow cuts are formed to achieve smaller gate spacing, then integration density is improved, but defects such as hallows and short-circuits occur
Solution Approach 1:
The patent extracts the problematic cut formation step from the manufacturing process. Instead of forming narrow cuts through the gate lines to isolate gates, the invention uses openings in the photoresist layer combined with sidewall spacers to achieve gate isolation without physically cutting the gate material, thereby eliminating hallow and short-circuit defects.
Solution Approach 2:
Sidewall spacers are introduced as an intermediary structure between the gate lines and the isolation regions. These spacers are formed on the sidewalls of the gate lines and provide the necessary electrical isolation without requiring direct cutting of the gate lines, thus preventing defects while achieving the required gate spacing.
3Quantity of substance
If the width of openings is reduced to form narrower cuts, then integration density is improved, but sidewall spacer material flows into the narrow cuts causing defects
Solution Approach 1:
Instead of forming narrow openings first and then trying to prevent material flow, the invention inverts the approach by forming wider openings and using sidewall spacers to define the final narrow gate spacing. The sidewall spacers are deposited conformally on the gate sidewalls, and their thickness controls the final gate pitch, eliminating the need to precisely control opening width at the smallest dimensions.
Solution Approach 2:
The invention changes the controlling parameter from opening width to sidewall spacer thickness. By controlling the thickness of the sidewall spacer material through deposition parameters rather than through lithographic opening width, the process achieves better precision and reduces material flow issues that occur when openings are made extremely narrow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables further integration density without physical cutting, reducing defects and enhancing the quality and stability of semiconductor devices by maintaining the integrity of gate lines and preventing material flow into narrow cuts.
Implementation Method 1
forming a self-assembly copolymer inside the openings
Implementation Method 2
followed by ion implantation to create insulating regions
Data Source
AI summary
The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention.