Self-Assembled Copolymer Templates for Sub-20nm Semiconductor Patterns
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Solution Overview
Problem
Conventional photolithography technologies face difficulties in fabricating nano-sized patterns smaller than 20 nm due to wavelength resolution limits, necessitating the development of new methods for forming fine nano-sized patterns in semiconductor devices.
Innovation Solution
A novel method using self-assembled materials, specifically copolymers with chemically different polymer blocks, to form nanostructures that can be used as templates for creating mask patterns, allowing for the formation of semiconductor device patterns with smaller diameters and increased compactness without requiring expensive advanced photolithographic equipment or complex processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used, then manufacturing process is simple, but pattern size cannot be smaller than 20 nm due to wavelength resolution limit
Solution Approach 1:
The patent introduces self-assembled block copolymer nanostructures as an intermediary template between conventional photolithography and the final nanoscale pattern. The photolithography step creates larger patterns that serve as templates for the self-assembly process, which then generates the sub-20nm patterns. This intermediary approach allows using existing photolithography equipment while achieving beyond its resolution limit.
Solution Approach 2:
The patent segments the pattern formation process into two distinct stages: (1) conventional photolithography to create initial template patterns, and (2) self-assembly of block copolymers to generate the final fine patterns. This segmentation allows each process to operate at its optimal scale, with photolithography handling the template and self-assembly handling the fine features.
2Manufacturing precision
If self-assembled material is used to form nanostructures, then pattern size smaller than 20 nm can be achieved, but manufacturing process becomes more complex
Solution Approach 1:
The patent employs self-assembled block copolymer materials that automatically organize into ordered nanostructures without requiring complex external control mechanisms. The molecules self-organize based on their inherent chemical properties, forming the desired patterns through spontaneous self-assembly rather than complex manufacturing processes.
3Area of moving object
If self-assembled material is used, then compactness of layout unit area increases, but manufacturing cost increases due to expensive materials and processes
Solution Approach 1:
The patent uses conventional photolithography patterns as an intermediary template that guides the self-assembly process. This allows the expensive self-assembly step to work within pre-defined boundaries, reducing material waste and process complexity compared to attempting self-assembly over the entire wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of semiconductor device patterns with smaller diameters and increased compactness beyond the resolution limits of conventional photolithography, facilitating the manufacturing of next-generation devices with improved layout efficiency.
Implementation Method 1
phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion
Data Source
AI summary
A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.


