Copper Bond Pad Structure for Low-Resistance Chip Interconnects
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Solution Overview
Problem
Existing bond pads in semiconductor chips face challenges with high contact resistance and reliability issues due to materials like aluminum and tungsten, which are prone to delamination and stress during etching, and have high resistance, limiting performance and stability, especially in low-profile applications such as micro-LEDs.
Innovation Solution
The integration of a bond pad structure comprising a copper-based vertical bond structure with a diffusion barrier layer and multiple conductive layers, including titanium nitride and tantalum nitride, reduces contact resistance and enhances reliability by mitigating material diffusion and etchant damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If aluminum or tungsten is used as bond pad material, then the bond pad can be formed with conventional materials, but the contact resistance increases and reliability decreases due to delamination and stress during etching
Solution Approach 1:
The bond pad structure uses a composite material system consisting of a copper base layer providing low contact resistance, overlaid with a titanium nitride barrier layer preventing copper diffusion, and topped with a tantalum nitride etch-resistant layer. This multi-material composite structure simultaneously achieves low contact resistance, high reliability, and etchant resistance that single materials cannot provide.
2Quantity of substance
If copper is used as the base layer to reduce contact resistance, then contact resistance decreases, but material diffusion to adjacent structures increases without a barrier layer
Solution Approach 1:
The titanium nitride layer serves as an intermediary barrier between the copper base layer and the surrounding environment. It prevents copper atoms from diffusing into adjacent dielectric or semiconductor structures while allowing the copper to maintain its low contact resistance function. This intermediary layer solves the harmful diffusion effect without compromising the beneficial low resistance property.
3Quantity of substance
If the bond pad structure is made taller to improve electrical performance, then contact resistance decreases, but the profile height increases which is unacceptable for low-profile applications
Solution Approach 1:
The invention changes the material parameters of the bond pad structure by using copper with inherently low resistivity (ρ ≈ 1.68×10^-8 Ω·m) as the base layer. This allows achieving low contact resistance with a shorter vertical profile compared to traditional aluminum or tungsten structures. The thin-film barrier and etch-resistant layers are optimized to minimal thicknesses to maintain electrical performance while minimizing height increase.
4Ease of manufacture
If conventional bond pad materials are used, then the manufacturing process is simple, but the bond pad is prone to delamination and stress during etching
Solution Approach 1:
The titanium nitride barrier layer and tantalum nitride etch-resistant layer are deposited on the copper base layer before any etching processes occur. This preliminary protective action prevents subsequent etchants from attacking the copper directly, eliminating delamination and stress issues that would otherwise occur during manufacturing. The barrier structure is built in advance to protect against future chemical attacks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases contact resistance, increases the reliability and stability of semiconductor chips by maintaining a low profile while ensuring structural integrity and resistance to etchant damage, thereby improving performance.
Implementation Method 1
a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure
Implementation Method 2
The vertical bond structure comprises a first conductive material (e.g., copper) having a relatively low resistance
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip having an interconnect structure overlying a substrate. The interconnect structure includes a conductive wire disposed in a dielectric structure. The conductive wire comprises a body structure. A passivation structure overlies the interconnect structure. A bond pad overlies the passivation structure. The bond pad comprises an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive wire. The lower bond structures respectively comprise a vertical bond structure and a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure. The upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer