Copper-Bonded Glass Modules for CTE-Matched Chip Packaging
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Solution Overview
Problem
Conventional semiconductor packages face limitations in scaling due to thermal expansion mismatch between organic resin and polymer substrates and silicon, leading to increased package size and cost, as well as inefficiencies in high-speed signal routing and power delivery.
Innovation Solution
The use of glass modules and substrates with copper bonding to create CTE-matched active circuitry, allowing for higher current density connections and reduced module dimensions, along with optimized through-glass vias for power delivery, facilitates efficient module-to-module communication and power transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional organic resin and polymer substrates are used in semiconductor packages, then ease of manufacture is improved, but thermal expansion mismatch with silicon causes increased package size and reduced reliability
Solution Approach 1:
The patent changes the material parameter (thermal expansion coefficient) by replacing organic resin and polymer substrates with glass substrates that have CTE values matched to silicon (2.6-3.3 ppm/°C), thereby resolving the thermal expansion mismatch problem while maintaining manufacturability
Solution Approach 2:
The patent uses composite material structures including glass substrates with copper interconnection layers and through-glass vias, combining materials with complementary properties to achieve both CTE matching and high electrical conductivity for reliable high-speed signal routing
2Ease of manufacture
If conventional substrates are used, then ease of manufacture is maintained, but signal routing efficiency and power delivery capability deteriorate
Solution Approach 1:
The patent replaces conventional trace-based electrical interconnects with three-dimensional vertical through-glass vias filled with copper, substituting the traditional planar routing mechanism with a vertical conduction path that enables higher current density and more efficient power delivery
Solution Approach 2:
The patent transitions from two-dimensional planar signal routing on substrate surfaces to three-dimensional vertical interconnection through the glass substrate, utilizing the depth dimension to create direct through-glass via paths that shorten current paths and improve signal routing efficiency
3Stability of the object's composition
If copper bonding is implemented for CTE matching, then thermal expansion compatibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary copper deposition and via formation in the glass substrate before final assembly, pre-establishing the copper interconnection paths and through-glass vias to simplify subsequent bonding operations and reduce overall manufacturing complexity
Solution Approach 2:
The glass substrate with integrated copper interconnections and through-glass vias serves multiple functions simultaneously: CTE matching with silicon, high-speed signal routing, and power delivery, consolidating what would otherwise require separate components into a single multi-functional element
4Productivity
If module dimensions are reduced for higher density, then bandwidth density is improved, but thermal management and signal integrity become more difficult
Solution Approach 1:
The patent changes the interconnection geometry parameter by implementing vertical through-glass vias that provide direct, short current paths with minimal resistance and inductance, maintaining signal integrity even as module dimensions are reduced for higher density configurations
Solution Approach 2:
The patent uses glass material with superior thermal and electrical properties compared to conventional organic substrates, providing stable signal transmission and effective thermal management in compact high-density module configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reduced package dimensions, increased bandwidth density, and efficient power delivery, addressing thermal expansion mismatch and signal routing inefficiencies, while supporting higher compute capabilities and memory bandwidth.
Implementation Method 1
The apparatus includes one or more dies, an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer including an interconnection layer formed on one side of the interposer, wherein the interconnection layer includes a plurality of copper interconnects
Implementation Method 2
bonding, via a copper bonding process, the first interconnection layer to a first top layer of the substrate
Data Source
AI summary
Copper-connected glass modules on a glass board are provided. An apparatus includes one or more dies, an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer comprising an interconnection layer formed on one side of the interposer, wherein the interconnection layer includes a plurality of copper interconnects, and a substrate comprising a top layer, glass core, and a bottom layer, wherein the interconnection layer of the interposer and the top layer of the substrate are copper bonded.