Copper-Bonded Memory Stacks for Higher HBM Bandwidth
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Solution Overview
Problem
Conventional high-bandwidth memory (HBM) systems face limitations in interconnection bandwidth and stack capacity due to the use of solder microbumps, which restrict the potential of copper-bonded memory stacks in achieving higher layer counts and energy efficiency.
Innovation Solution
The implementation of copper-bonded interconnection systems, including hybrid copper-bonded bridge-connected memory stacks, passive hybrid copper-bonded bridge connections, and overlapping buffer-die configurations, to increase interconnection bandwidth and stack capacity by replacing solder microbumps with copper bonding, thereby reducing thermal resistance and parasitic impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If solder microbumps are used for interconnection, then manufacturing process is simpler, but interconnection bandwidth and stack capacity are limited
Solution Approach 1:
The patent changes the bonding material from solder to copper, fundamentally altering the interconnection medium's physical and electrical parameters. This enables higher interconnection bandwidth and stack capacity while managing the increased bonding process complexity through controlled parameter changes in the copper bonding process
Solution Approach 2:
The patent employs hybrid copper-bonded structures that combine copper interconnection layers with traditional solder bump interconnections in specific configurations. This composite approach allows copper bonding to provide high-bandwidth paths while solder bumps handle other interconnection requirements, achieving enhanced bandwidth without fully committing to complex copper-only bonding processes
2Temperature
If copper bonding is used to increase stack height, then thermal resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediary structures such as buffer dies, support dies, and alignment marks that facilitate precise copper bonding at increased stack heights. These intermediaries act as reference frames and mechanical supports, enabling the required bonding alignment precision while allowing thermal benefits of copper bonding to manifest across taller stacks
Solution Approach 2:
The patent performs preliminary alignment and positioning operations before the actual copper bonding process. Alignment marks are pre-formed on dies, and bonding fixtures are pre-configured to ensure precise positioning. This preliminary action ensures that when copper bonding occurs at increased stack heights, the required manufacturing precision is achieved without rework
3Use of energy by moving object
If solder microbumps are replaced with copper bonding, then energy efficiency increases, but interconnection pitch density must be increased
Solution Approach 1:
The patent transitions from two-dimensional planar interconnections to three-dimensional vertical interconnections through stacked memory architectures with copper bonding. This dimensional change allows interconnection pitch to be effectively increased in the vertical dimension, compensating for the reduced lateral pitch density while maintaining or improving energy efficiency through shorter current paths and lower resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases interconnection bandwidth and stack capacity, enabling the realization of thinner silicon layers and higher energy efficiency, while allowing for more layers in the stack, thus enhancing the performance and functionality of memory systems.
Implementation Method 1
copper bonding can provide much denser interconnection pitch compared to solder microbumps, while also reducing the thermal resistance and parasitic electrical impedance between the bonded die
Implementation Method 2
copper bonding can provide much denser interconnection pitch compared to solder microbumps, while also reducing the thermal resistance and parasitic electrical impedance between the bonded die
Data Source
AI summary
A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.