Copper Bump Redistribution Structure Without Embedded Via Pads
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Solution Overview
Problem
The use of embedded via pads in redistribution structures for forming copper bump structures can lead to warpage, resulting in interconnection failures and electrical yield loss due to high interfacial resistance and the formation of electrical opens.
Innovation Solution
An organic interposer is manufactured using a redistribution layers-first (RDL first) process without embedded via pads, reducing warpage and enhancing electrical characteristics by minimizing seed layer interfaces and intermetallic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If embedded via pads with seed layers are used in redistribution structures, then copper bump structures can be formed, but stacking warpage occurs resulting in interconnection failures and electrical yield loss
Solution Approach 1:
The patent removes the embedded via pad structure with its seed layer from the redistribution layer. Instead, copper bumps are formed directly on the redistribution layer using a different copper deposition method (electroless plating followed by electroplating), eliminating the source of warpage while maintaining copper bump formation capability
Solution Approach 2:
The patent changes the copper deposition parameters and method - using electroless plating to initiate copper growth directly on the redistribution layer without requiring a separate seed layer, then followed by electroplating to build up the copper bump structure. This parameter change eliminates the warpage-causing seed layer while enabling copper bump formation
2Ease of manufacture
If embedded via pads with seed layers are used, then copper bumps can be formed, but electrical yield is reduced due to high interfacial resistance and formation of electrical opens
Solution Approach 1:
The patent extracts and removes the problematic seed layer interface that causes high interfacial resistance and electrical opens. By forming copper directly on the redistribution layer through electroless plating, the patent eliminates the additional interface between seed layer and copper, improving electrical connection quality
Solution Approach 2:
The patent applies a preliminary copper adhesion layer through electroless plating before electroplating the copper bump. This preliminary action ensures excellent adhesion and low interfacial resistance from the start, preventing electrical opens and improving electrical yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces stacking warpage and increases electrical yield by eliminating the extra layer caused by embedded seed layers, thereby improving the reliability of semiconductor structures.
Implementation Method 1
forming three-dimensional (3D) electroplated copper bumps directly on the planar metal interconnects
Data Source
AI summary
First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.