Non-volatile Memory Device Using Copper-Chalcogenide Interface
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Solution Overview
Problem
Current non-volatile memory devices face limitations in scalability and power consumption due to high switching currents and voltages, particularly in flash memory devices, and stability issues with programmable metallisation cell technology.
Innovation Solution
A memory device using a copper layer in contact with a metal-doped SbTe chalcogenide material, switching between resistance states with voltage differences of 0.5 volts or less, achieving low power consumption and high resistance states through an interfacial layer mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices use higher memory density, then storage capacity increases, but individual memory cell size decreases leading to scaling problems
Solution Approach 1:
The patent changes the fundamental operating parameter from charge storage (flash memory) to resistance switching (memristive device), enabling scaling to smaller dimensions without the physical limitations that constrain flash memory cells at high densities
Solution Approach 2:
The patent replaces the mechanical/physical structure of floating gate transistors with a nanoscale memristive structure consisting of a switching layer and electrode, enabling further miniaturization beyond the 45nm node where flash memory faces fundamental physical limitations
2Speed
If phase-change memory devices use higher switching currents, then switching speed improves, but power consumption increases
Solution Approach 1:
The patent changes the switching mechanism from thermal (phase-change) to electrical (resistance switching), allowing state transitions at lower currents and voltages while maintaining fast switching speeds through direct electron transport control in the nanoscale switching layer
Solution Approach 2:
The patent creates a localized switching region at the Cu-Chalcogenide interface with unique electrical properties, confining the high-current density effect to a small volume and enabling low-power operation overall while achieving rapid switching in the active region
3Use of energy by moving object
If programmable metallisation cell memory uses lower switching voltages, then power consumption decreases, but data retention stability deteriorates
Solution Approach 1:
The patent uses a composite structure combining Cu electrode with Chalcogenide switching layer, creating an interfacial region with specific properties that enables both low-power switching and stable data retention, overcoming the stability issues of PMC memory while maintaining low voltage operation
Solution Approach 2:
The patent introduces an interfacial layer between Cu and Chalcogenide materials that acts as an intermediary region, mediating between the electrode and active material to enable stable resistance states and reliable data retention at low operating voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low power consumption and high resistance switching with significantly reduced voltage requirements, overcoming scalability and stability challenges in existing technologies, and offering a distinct switching mechanism compared to programmable metallisation cells.
Implementation Method 1
Resistive-switching memory devices store information by inducing changes in the resistance of an active material, usually through the application of specific currents or voltages
Implementation Method 2
Information may be stored in a cell of the device by applying current-induced heat to switch the chalcogenide material from a low resistance, crystalline state to a high resistance, amorphous state
Data Source
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Figure 3(a)~4
Figure 5
AI summary
A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less. The current flow when switching between resistance states is less than 10μA. The memory cells of the device can be toggled between the resistance states, and the resistance states are non- volatile.