Copper Cuboid QFN Package for Stacking and Thermal Management
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Solution Overview
Problem
Existing semiconductor devices, particularly chip-scale stacked packages, face challenges in achieving a thin profile due to wire looping and multi-layer package designs, which hinder miniaturization and increase fabrication costs, while also struggling to provide improved thermal and electrical performance and compatibility with chips of different characteristics.
Innovation Solution
A semiconductor device is assembled on a copper cuboid without a cavity, with reduced interconnecting line lengths, allowing direct heat-spreading attachment and reduced device profile, using a method that involves copper cuboids with aligned back surfaces and metal-filled vias for stacking, and a fabrication process that includes selective plating and etching to minimize wire connections and device thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect chip contact pads with package terminals, then electrical connection is achieved, but the mechanically weak heat-affected zone necessitates vertical wire positioning leading to high looping and increased device height
Solution Approach 1:
The patent inverts the conventional wire bonding approach by positioning the wire bond horizontally within the package plane rather than vertically. The wire connects chip contact pads to package terminals through a planar routing path, eliminating the need for high looping and reducing device height while maintaining electrical connection reliability
Solution Approach 2:
The patent transitions from three-dimensional vertical wire bonding to two-dimensional planar wire routing. By laying wires flat within the package plane and using multiple conductive layers, the design achieves electrical connections without vertical height increase, effectively moving the problem from the vertical dimension to the horizontal plane
2Adaptability or versatility
If multi-layer package design is used to enable solder ball connection, then external connection is achieved, but the design increases device height and fabrication complexity
Solution Approach 1:
The patent makes the package substrate multi-functional by integrating both wire bond routing and solder ball connection capabilities within a single-layer or minimal-layer structure. The substrate serves simultaneously as the mechanical support, electrical interconnection medium, and external connection interface, eliminating the need for separate multi-layer constructions
Solution Approach 2:
The patent merges the functions of wire bond interconnection and solder ball attachment into a unified package structure. The conductive traces on the substrate serve dual purposes: routing signals from chip pads to wire bonds and providing solderable terminals for external connections, thereby reducing overall package complexity
3Ease of manufacture
If cavity-down package is used for chip assembly, then chip mounting is achieved, but the approach requires adhesive attachment and increases device height
Solution Approach 1:
The patent extracts the chip from the conventional cavity-down configuration and positions it in a cavity-up orientation. This extraction from the traditional mounting approach allows the chip to sit flush with or slightly above the package surface, eliminating the need for deep cavities and adhesive layers that increase height, while simplifying the assembly process
4Ease of manufacture
If existing cavity-down package is used, then chip assembly is achieved, but it is difficult to bring heat-conducting metal pieces into contact with the semiconductor chip
Solution Approach 1:
The patent inverts the thermal management approach by placing heat-conducting metal pieces in direct contact with the chip's bottom surface in a cavity-up configuration. This inversion allows thermal pathways to be established from the chip through the substrate to external heat sinks, dramatically improving heat dissipation compared to cavity-down designs where thermal contact is difficult to achieve
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a low-cost, robust semiconductor device with enhanced thermal performance, reduced thickness, and minimal electrical resistance and inductance, suitable for high-speed applications and flexible design variations.
Implementation Method 1
Encapsulation compound is adhering to and embedding the chip, the wire bonds, and the sides of all cuboids
Implementation Method 2
A semiconductor device is assembled on a copper cuboid... allowing direct heat-spreading attachment
Implementation Method 3
Solder elements of about equal size are connecting each via metal of the first device with the matching via metals of the second device
Implementation Method 4
silver is selectively plated to define areas intended for chip attach and wire bond
Implementation Method 5
The unprotected to aluminum layer is then removed, and the exposed copper layer is also etched to a pre-determined second thickness
Data Source
AI summary
A semiconductor device comprising a semiconductor chip (101) assembled on a first copper cuboid (110); the cuboid has sides of a height (111). The device further has a plurality of second copper cuboids (120) suitable for wire bond attachment; the second cuboids have sides of a height (121) substantially equal to the height of the first cuboid. The back surfaces of all cuboids are aligned in a plane (130). Encapsulation compound (140) is adhering to and embedding the chip, the wire bonds, and the sides of all cuboids so that the compound forms a first surface (140b) aligned with the plane of the back cuboid surfaces and a second surface (140a) above the embedded wires. For devices intended for stacking, the devices further comprise a plurality of vias (160) through the encapsulation compound from the first to the second compound surfaces; the vias are filled with copper, and the via locations are matching between the devices-to-be-stacked.