Copper Electroplating Suppressor for Void-Free Submicron Filling
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Solution Overview
Problem
In microelectronics manufacturing, copper electroplating faces challenges such as overplating, microvoids, and surface protrusions in small, high-aspect-ratio interconnect features, which affect the yield and quality of semiconductor devices due to uneven growth rates and seed layer coverage.
Innovation Solution
A copper electroplating composition and method using a suppressor compound with polyether groups covalently bonded to a cationic species, such as a nitrogen-containing amine, which enhances the distribution of current and suppresses copper deposition, allowing for rapid bottom-up growth and reduced voiding in submicron-sized features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electrolytic Cu plating is used to fill submicron-sized interconnect features, then Cu deposition occurs, but overplating and surface protrusions form due to uneven growth rates
Solution Approach 1:
The patent applies a suppressor compound that selectively adsorbs to different regions of the substrate, creating locally different deposition rates. The suppressor preferentially suppresses Cu deposition on planar surfaces while allowing enhanced deposition in interconnect features, achieving uniform filling without overplating on flat areas
Solution Approach 2:
The patent modifies the electroplating bath composition by introducing a suppressor compound and adjusting plating parameters (current density, temperature, pH) to control the deposition kinetics. These parameter changes enable differentiation between feature filling and surface deposition rates, preventing overplating while ensuring complete feature fill
2Reliability
If rapid bottom-up growth is achieved in high aspect ratio features, then void formation is reduced, but control over deposition uniformity becomes more difficult
Solution Approach 1:
The suppressor compound acts as an intermediary that mediates between the electrochemical deposition process and the substrate surface. It selectively adsorbs to control current distribution, promoting uniform current density at the bottom of high aspect ratio features where it is most needed, thereby enabling rapid void-free filling while maintaining overall deposition control
Solution Approach 2:
The patent employs pulsed or periodic plating cycles that alternate between deposition and suppression phases. This periodic action allows the suppressor to adsorb and desorb in a controlled manner, maintaining rapid bottom-up growth while preventing excessive deposition and ensuring uniformity across different feature types
3Manufacturing precision
If Cu is deposited to ensure complete filling of small interconnect features, then interconnect reliability improves, but overplating occurs on surrounding planar surfaces
Solution Approach 1:
The suppressor compound creates locally different deposition conditions by selectively adsorbing to planar surfaces versus interconnect features. This local differentiation ensures that Cu deposition is enhanced only where needed (in features) while being suppressed on surrounding planar areas, achieving complete feature filling without excessive Cu deposition elsewhere
Solution Approach 2:
The patent applies a controlled amount of suppressor compound that provides partial suppression on planar surfaces while allowing excessive (rapid) deposition in interconnect features. This partial action approach ensures complete feature fill is achieved without the harmful excess Cu that would result from uniform suppression across the entire substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves faster and more uniform copper deposition into small, high-aspect-ratio features, reducing voids and overplating, and improving the quality of copper surfaces, thereby enhancing the yield and reliability of semiconductor manufacturing.
Implementation Method 1
a suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species
Implementation Method 2
electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features
Data Source
AI summary
An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.