Copper Gate Electrode Buffer Layer for TFT Signal Integrity
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Solution Overview
Problem
The use of copper as a gate electrode in thin film transistors leads to reactivity issues when exposed to plasma enhanced chemical vapor deposition, causing adhesion and interaction problems with silicon oxide or silicon nitride gate insulating layers, resulting in signal delay and pulse distortion in larger liquid crystal displays due to high gate line resistance.
Innovation Solution
A microcrystal material layer, such as a silicon layer, is deposited and treated with plasma to form a buffer layer on the copper gate electrode, which is then covered with a gate insulating layer using plasma enhanced chemical vapor deposition, preventing reactivity and ensuring proper adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as the gate electrode to reduce resistance, then electrical conductivity is improved, but reactivity with plasma enhanced chemical vapor deposition atmosphere causes adhesion and interaction problems
Solution Approach 1:
A buffer layer is introduced as an intermediary between the copper gate electrode and the plasma enhanced chemical vapor deposition atmosphere. This buffer layer prevents direct contact and reaction between the copper and reactive species in the plasma, thereby maintaining the low resistance benefit of copper while eliminating its harmful reactivity with the deposition atmosphere.
Solution Approach 2:
The buffer layer is formed in advance before the plasma enhanced chemical vapor deposition process. This preliminary protective action prevents the copper gate electrode from being exposed to and reacting with the plasma atmosphere during subsequent deposition steps, thereby preventing adhesion and interaction problems before they can occur.
2Productivity
If copper gate electrode is exposed to plasma enhanced chemical vapor deposition atmosphere, then gate insulating layer can be deposited, but copper reacts with free radicals causing silicon oxide detachment or silicon nitride bubbling
Solution Approach 1:
The buffer layer serves as a protective intermediary that allows the plasma enhanced chemical vapor deposition process to proceed while preventing direct interaction between the plasma and copper gate electrode. This enables continuous deposition of gate insulating layers without the harmful reactions that would compromise film integrity.
Solution Approach 2:
The buffer layer is formed beforehand to provide protection during the deposition process. This preliminary protective measure ensures that when plasma enhanced chemical vapor deposition occurs, the copper gate electrode is already shielded, preventing reactions that would cause silicon oxide detachment or silicon nitride bubbling.
3Area of stationary object
If gate lines are made longer to increase display size, then display area is increased, but signal delay and pulse distortion increase due to high resistance
Solution Approach 1:
The electrical resistance parameter of the gate lines is changed by using copper material instead of conventional materials. This parameter change enables longer gate lines to be used in larger displays while maintaining acceptable signal transmission quality, as copper's superior conductivity compensates for the increased length and associated resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer layer effectively protects the gate electrode from reactivity with subsequent deposition processes, reducing signal delay and pulse distortion by maintaining low resistance in gate lines, thus enhancing the performance of thin film transistors in larger liquid crystal displays.
Implementation Method 1
The gate electrode 103 is deposited on the insulating substrate 102 using a physical vapor deposition (PVD) process
Implementation Method 2
the gate insulating layer 104, the active channel layer 105, n+ type semiconductor layer 106, and a metal layer 107 are sequentially deposited in a chamber using a plasma enhanced chemical vapor deposition (PECVD) process
Data Source
AI summary
A method of forming a thin film transistor comprising a deposition procedure of a microcrystal material layer and performing a plasma treatment procedure. The deposition procedure and the plasma treatment procedure are repeated. A buffer layer is thus formed on the gate electrode.