Copper Inductor Fabrication with Silicon Nitride Sidewalls
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Solution Overview
Problem
The development of integrated circuits is hindered by the limited availability of low-loss inductor structures, particularly at high frequencies, due to high resistive losses and low quality factors in copper inductors, which are exacerbated by parasitic capacitances and resistive losses, necessitating improved methods for forming copper lines with smooth and vertical sidewalls.
Innovation Solution
A method involving the formation of copper inductors with smooth and vertical sidewalls by using a copper barrier/seed layer, electroplating, annealing, and anisotropic etching to reduce grain size and resistivity, combined with the use of silicon nitride sidewalls for profile control and protection during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as the conductive material to replace aluminum, then electrical conductivity and resistance to electromigration are improved, but the etching process becomes difficult due to copper's inability to readily form volatile species
Solution Approach 1:
A barrier layer is introduced as an intermediary between the copper interconnect line and the etching environment. This barrier layer prevents copper from directly interacting with etchants, thereby enabling the etching process to proceed effectively while maintaining copper's superior electrical properties and electromigration resistance
Solution Approach 2:
The invention changes the physical and chemical parameters of the copper deposition process, including controlling grain size through specific deposition conditions and using annealing treatments. These parameter changes enable copper to form a structure that is more amenable to subsequent processing while maintaining its excellent electrical conductivity
2Length of moving object
If thin conductors are used to reduce device dimensions, then device miniaturization is achieved, but resistive losses increase leading to lower quality factors
Solution Approach 1:
The invention changes the microstructural parameters of the copper conductor by controlling grain size and crystallographic orientation. By depositing copper under specific conditions and applying annealing treatments, the grain size is reduced to a controlled range that minimizes resistive losses while allowing the use of thin conductor dimensions for device miniaturization
Solution Approach 2:
The invention creates local quality variations in the copper structure by controlling grain size and orientation in different regions. The copper interconnect line is engineered to have specific grain structures that optimize electrical conductivity in the direction of current flow, thereby reducing resistive losses in the critical current-carrying regions
3Ease of manufacture
If conventional copper deposition methods are used, then copper lines can be formed, but sidewall roughening and undercuts occur during processing
Solution Approach 1:
The invention changes the deposition parameters to control grain growth and crystallographic orientation during copper formation. By adjusting deposition temperature, pressure, and composition, the copper is deposited with a controlled grain structure that resists sidewall roughening and undercut formation during subsequent processing steps
Solution Approach 2:
The invention performs preliminary actions during the copper deposition process to prevent future processing problems. The copper is deposited with specific grain structures and orientations that pre-establish resistance to sidewall roughening and undercutting, eliminating the need for corrective measures in later processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in copper inductors with reduced resistivity, improved RF performance, and increased quality factors, enabling more efficient signal propagation and higher frequency operations by minimizing sidewall roughening and undercuts, thus enhancing the performance of integrated circuits.
Implementation Method 1
forming a copper barrier/seed layer over the passivation layer and the plurality of openings
Implementation Method 2
electroplating, annealing, and anisotropic etching to reduce grain size and resistivity
Implementation Method 3
electroplating, annealing, and anisotropic etching to reduce grain size and resistivity
Implementation Method 4
combined with the use of silicon nitride sidewalls for profile control and protection during processing
Data Source
AI summary
A method of forming one or more inductors on a substrate is disclosed. The method includes forming a first dielectric material over the substrate, forming a trench in the first dielectric material, and substantially filling the trench with copper to form the one or more inductors. The first dielectric material is removed and a second dielectric material is formed over the copper. The second dielectric material is removed from an uppermost portion of the copper, thus leaving a portion of the second dielectric material on the sidewalls of the copper.