Copper Interconnect Annealing for Hillock Reduction
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Solution Overview
Problem
As integrated circuit features shrink, closely packed conducting portions lead to issues like cross-talk noise, power dissipation, and copper hillock defects, which reduce device yield and performance.
Innovation Solution
A method involving a semiconductor substrate with a copper interconnect structure subjected to an anneal process in an inert environment within a deposition chamber, followed by depositing a dielectric layer, to reduce copper hillock defects and improve device yield and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as interconnect wires to improve conductivity, then electrical performance is improved, but copper hillock defects occur reducing manufacturing yield
Solution Approach 1:
The patent changes the stress state parameter of the copper interconnect structure by performing an anneal process that transforms the copper from a first stress characteristic to a second stress characteristic, thereby reducing copper hillock defects while maintaining electrical performance
Solution Approach 2:
The anneal process is performed as a preliminary action before depositing subsequent dielectric layers, modifying the copper stress state in advance to prevent hillock formation during later processing steps
2Manufacturing precision
If multiple processing steps are performed separately to reduce defects, then manufacturing precision is improved, but process complexity and time increase
Solution Approach 1:
The patent merges the anneal process with the deposition chamber operations by maintaining the substrate in the deposition chamber after annealing and directly depositing dielectric layers without intermediate removal, thereby reducing process complexity while maintaining defect reduction benefits
Solution Approach 2:
The substrate remains continuously in the deposition chamber from the anneal process through dielectric layer deposition, eliminating interruptions and maintaining a continuous useful action that reduces both time and process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anneal process reduces copper hillock defects, enhancing device yield and performance by maintaining the substrate in the deposition chamber for subsequent dielectric layer deposition, eliminating the need for intermediate removal and improving interconnect structure integrity.
Implementation Method 1
The semiconductor substrate including the copper interconnect structure is subjected to an anneal process in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic
Data Source
AI summary
A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an intermetal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.