Copper Interconnect Dual Layer Cap Electromigration Resistance
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Solution Overview
Problem
Existing microelectronic interconnects face challenges in enhancing electromigration resistance without increasing interconnect resistance, particularly as interconnect line widths shrink, and the segregation of impurities to the dielectric cap/Cu interface is limited, leading to void formation and increased resistance.
Innovation Solution
Creating lattice defects at the surface of copper interconnects to drive impurity segregation to that region, allowing for a higher atomic percentage of impurities without increasing resistance, through a dual layer structure comprising a metallic and metal oxide portion, and using manganese oxide and metallic manganese layers to enhance electromigration lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity is introduced in copper seed layer to improve electromigration resistance, then electromigration lifetime is improved, but interconnect resistance increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform impurity distribution in the copper interconnect structure. Impurity atoms are engineered to segregate specifically at the copper-dielectric interface region through controlled oxidation and stress-induced diffusion, while the bulk copper remains relatively pure. This localized impurity concentration at the interface improves electromigration resistance without significantly increasing bulk interconnect resistance, resolving the contradiction between reliability improvement and resistance increase.
Solution Approach 2:
The patent utilizes parameter changes by controlling the oxidation state of impurity atoms at the interface. By applying thermal stress and controlled oxidation conditions, impurity atoms transition from metallic state to oxidized state at the interface, creating a gradient in chemical composition and oxidation state. This parameter change enables impurity segregation to the interface region, improving electromigration lifetime while minimizing bulk resistance increase.
2Reliability
If greater amount of impurity is used to increase electromigration lifetime in narrower interconnects, then electromigration resistance is improved, but interconnect resistance increases further
Solution Approach 1:
The patent addresses scaling challenges by enhancing the local quality approach for narrower interconnects. As line widths decrease, the patent increases impurity segregation efficiency at the interface through controlled stress application and oxidation, ensuring that impurity concentration is maximized locally at the copper-dielectric interface while maintaining lower bulk impurity levels. This allows the structure to maintain improved electromigration lifetime in scaled-down geometries without proportionally increasing resistance.
Solution Approach 2:
The patent introduces a vertical dimension to impurity distribution by creating a depth-dependent impurity concentration profile. Through stress-induced diffusion and controlled oxidation, impurity atoms are driven vertically toward the copper-dielectric interface, creating a gradient where impurity concentration increases with depth from the top surface to the interface region. This vertical segregation in the depth dimension allows effective electromigration protection in narrow interconnects without requiring proportional increases in bulk impurity content that would increase resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual layer structure effectively increases electromigration lifetime by segregating more impurities to the surface, reducing their presence in the bulk conductor and thus minimizing resistance increases, while being scalable for narrower interconnects.
Implementation Method 1
stressing a top region of the bulk conductor or creating defects at a top region of the bulk conductor
Implementation Method 2
drive impurity (dopant) segregation to that region
Implementation Method 3
thermally treating the substrate thereby forming an impurity containing oxide layer and a metallic impurity layer at the top region of the bulk conductor
Implementation Method 4
forming an impurity containing oxide layer
Data Source
AI summary
A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.